simulation loop timing

[Pangolin]

I am having trouble runnnig my simulation in real time.  I am using LabVIEW version 10.0F2 and acquiring signals using a PCI-6230. In the simulation loop parameters, I am using the solver: Runga-Kutta 1 (Euler) with a step size of 0.005, and in the timing parameters I have it syncronized with the timing source, source type: 1 KHz clock with a period of 5.For a relatively simple VI these settings seem to work just fine. In a slightly more complicated VI, which happens to be saved as a Simulation SubVI for another VI, I see that the loop timing is completely off. Also by removing components of the subvi the timing changes drastically. Please advise.

[mahu]

The timing characteristic of a simulation is very difficult for a pc. Maybe with some practices you can improve the execution, like this:

http://zone.ni.com/devzone/cda/tut/p/id/5686

but to help, need see some of your code.

Regards

[dbohls]

From the information you've provided, it sounds to me like you've set everything up correctly to run real-time at 200 Hz. Of interest at this point is what is inside the loop. Maybe something is causing it to finish late. Condsider dropping down a "simulation parameters" block and then unbundle the output. See if the "finished late?" boolean is ever getting set. What appears to be happening to the timing? Does it seem to be taking more than 5 milliseconds? Is there lots of jitter?