punctured viterbi decoding using Xilinx IP core for LAbview FPGA 2014

[incisive]

HI

I want to apply viterbi decoding to my 3/4 punctured stream using xilinx IP core for labview fpga.

I read that for punctured of viterbi decoder v.7, depuncturing has to be external. Is there a code for depuncturing available?

What is the purpose of erasure flag?

I have to first append zeros in places where punturing is done?

How should I set the rate? Is there a design example available for hard coded 3/4 punctured viterbi decoder. Constraint length 7. If so please share. 

[Dennis_Knutson]

Duplicate - http://forums.ni.com/t5/LabVIEW/punctured-viterbi-decoding-using-Xilinx-IP-core-for-LAbview-FPGA/td-...

[incisive]

Has anyone ever be successful in implementing Hard decoded viterbi decoding with depuncturing? All the posts I have read so far, nobody was able to implement it successfully.

Please share if you are able to run your depunctured code.