Let's take a high level look at the RIO architecture.
You have three general components: FPGA, RT, Host PC
The FPGA is responsible for handling all of the IO. Even if you skip the FPGA, LV will create a bitfile for you to handle the IO only portion. But, at the base, you're going to have all of your IO come directly from the FPGA simply because that's what it's hooked up to.
As the FPGA is a hardware implementation, it doesn't always make sense to handle all of your IO processing here. But, it's still nice to have the strength of a RT OS. This is where your RT comes in. You can process the IO without actually modifying it directly. You do this by passing things back and forth from the FPGA to the RT through means like User Defined Variables or more commonly FIFO buffers (please make it a habit to use the latter when possible) You can leverage this functionality to get the data from the FPGA and then do all of the analysis you'd like on the RT.
When you want to see things on your PC, you need to send data back and forth from the RT (or the FPGA) to the Host PC. You'd use things like Network Published Shared Variables or Network Streams to accomplish this task.
When he's saying put all of the IO on the FPGA, it's because if you try to split the IO between the RT VI and the FPGA VI, you're telling the RIO that you need to have two separate hardware implementations running on the FPGA at once. That simply can't happen. You just need to take some time to understand how to pass data from the FPGA to the RT so that you can use that to make changes to your values. Once you have that in place, you can put all of the IO on the FPGA and still gain the value from the RT.
