integration and differential on labview fpga

[NoveltyHan]

Hello! Now I want to achieve integration and differential on labview fpga .but I don't know how 

So someone really good at it ,Please help me!

Better with the block diagram

[GerdW]

Hi Han,

in a very simplistic view:

- "integration" means to add up the inputs over time (x axis)

- "differentiation" means to get the differences between samples

Where exactly do you have problems with?

[NoveltyHan]

I don't know how achieve it in the SCTL in the labview fpga .

If you can do it ,please write a FPGA VI for me 

Thanks~

[GerdW]

Hi Han,

when you want someone to do your work you should post in the "job openings" forum.

Otherwise show what you have tried so far and tell us, where you get stucked!

[NoveltyHan]

sorry,I'm a freshman here .

I will show you what I have tried in the following picture

because in the fpga vi I can't use the integration and differention vi ,so I have to  write the alogrithm by myself . and I'm stucked at how to substract  a number from the previous number in the array.

because we can't use shift register or feedback node in the for loop which in the SCTL 

I have tried the way just like the picture following ,but the mistake is the feedback node and divide 

[crossrulz]

Just to clear things up here, are you trying to do some PID control or are you looking to actually do the calculus processing for something else?

And since we are talking about analog signals (would make little to no sense with digital), your read of the signal cannot be in a SCTL (takes way more than a single clock cycle to get a measurement from an analog input on any C series modules I know of).

So, please, show us what you have and we can help direct you to fix it yourself.  We are here to help people figure things out, not do it for them.  After all, I have my own job to do.

[crossrulz]

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@NoveltyHan wrote:

I have tried the way just like the picture following ,but the mistake is the feedback node and divide 

---

Divides are not allowed in a SCTL since they take multiple clock cycles to perform.  You may be able to get away with a multiplication by the inverse (cannot tell what you are dividing since the image is incomplete).

But taking a step back, do you really need this to be in a SCTL?  What are your timing requirements?  What hardware are you using?  Where are these signals coming from?

[NoveltyHan]

I do read the singal  in the SCTL with PXI-5170r ,I want to do some singla processing in the fpga and translate it to the host VI,so I can improve the throughout rate but don't how to achieve 

because I can't use the integration and differential vi in the fpga vi,so i have to write the algrothm by myself ,and I don't know how substract a number from the previous number in the array, we can't use the shift register or feedback node in the for loop which in the SCTL.

I have tried just like the pic following ,and mistakes are feedback node and division

[NoveltyHan]

Because I get the singal from the sample data in :channel 0 to 3,channel 3 is used for trigger ,so the singal is from the channel 0 to 2, and the fpga I/O channel 0 to 3 is in the SCTL ,the example vi just do like this ,and the timing is data clock I don't know what does this means