how to synchronize cRIO-9067 to IEEE 1588 under FPGA structure within nanoseconds?

[user48625]

Hi,

I plan to use IEEE 1588 to synchronize compactRIO-9067, and I found out this thread,

1588 synchronization of distributed cRIO systems

But the topic in that thread is synchronizing FPGA to RT system clock, and I know that the accuracy of RT can be 1 microsecond extremely.

However, I need an accuracy under 1 microsecond (~ns), and I know that the accuracy of FPGA can be nanoseconds, so can I trigger FPGA with 1588 message?

My purpose is not to calibrate system clock on RT, rather than to count for FPGA loop, that is, to ensure the jitter of every loop to be under 1 microsecond.

So the whole concept is to calibrate the counter on FPGA to ensure the accuracy of every count.

Is it possible to trigger FPGA loop with IEEE 1588 message?

Thanks!   

Shang-Che.

[speleato]

Hi Shang-Che,

I don't think this is exactly what you are asking for, but maybe it helps you solve your problem. Have you seen the FPGA Timekeeper NILabs release? https://decibel.ni.com/content/projects/ni-timesync-fpga-timekeeper

Sebastian