fpga

[mahmoud12]

Hello,

I want to tell me  if it is allowed to use a FPGA I/O nodes in Single-Cycle timed loop ? if the answer is "yes", how does  this node work inside timed loop if this 

node contains a VHDL code (sequential and combinatorial) ?

[mahmoud12]

and if it is allowed to use a FIFO in Single-Cycle timed loop ??

[Simon_T]

Hi,

You can use FPGA I/O nodes in single cycle timed loops, with limitations:

http://zone.ni.com/reference/en-XX/help/371599G-01/lvfpga/fpga_timed_loop/

You can use FIFO-s in single sycle timed loops for sure. In fact, you can use it between them for passing data, I would recommend them as the solution for crossing clock domains:

http://zone.ni.com/reference/en-XX/help/371599G-01/lvfpgaconcepts/implementing_domains/

For using VHDL code in a single sycle timed loops, it can only contain combinatorial logic. If you have sequential logic, you will get an error message after the compilation

http://digital.ni.com/public.nsf/allkb/722A9451AE4E23A586257212007DC5FD

Best Regards,

Simon

[mahmoud12]

my code is sequential logic, so what is the method to implement my code inside timed loop using CLIP? what is the result if I put my code inside while loop ??

[Simon_T · Accepted solution]

You can cut your code to pure combinatorial sections by rplacing your registers with LabVIEW "shift registers" on the single cycle timed loop. This way you basically implement pipelined logic.

Optimizing your LabVIEW FPGA VIs: Parallel Execution and Pipelining

You can find help about using CLIP nodes in these articles:

Using VHDL Code With LabVIEW FPGA

Importing External IP Into LabVIEW FPGA

Regards,

Simon