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Is it possible to change DRAM burst length on PXIe-7965R? I suppose that burst length is 8. Since i have 4 data words available for burst write to the same row i don't want to waste time in longer bursts (throughput is critical). I want to open 4 rows, one per each bank, burst 4 data words to each of them, precharge banks, and then open another 4 rows in different banks. Can i do this?

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Hi Stevan, and welcome to NI forums!

 

If I understand correctly, you are doing high throughput writes to the onboard memory of the 7965R card.

 

The DRAM of the PXIe-7965R is connected to the FPGA with a 128 bit wire connection on which simultaneous reads and writes are available (since it's DDR, so both rising and falling clock edges are usable) The maximum theoretical throughput is 1.6 GB/s. For optimal performance, a Random Acces CLIP configuration is the best. You can find some good examples on using high throughput DRAM use in Examples>>Hardware Input and Output>>FlexRIO>>External Memory.

 

Also please check out these links on FPGA DRAM performance.

 

How many bits of data would you like to write/read at once? What is your desired throughput? 

 

Kind regards:

 

Andrew Valko

NI Hungary

 

 

Andrew Valko
National Instruments Hungary
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