Hi,
I am using DMA FIFO (host to target) to read all the elements in the FIFO, so I read a value and I save it in register (the register exists in FPGA I/O Nodes using CLIP so the code was written in VHDL). The VHDL code is written to read a new value from the FIFO every clock and save it in regiter, I put the both ( FPGA I/O Nodes and the FIFO) in timed loop but after run I don't obtain the same value in the FIFO so the register has a wrong value .... so what is the method to do this ? what is the method to synchronize the transfer of data between FIFO and FPGA I/O Nodes (because in my code I want to read a value from the FIFO and save it in register and read the next value ... to read all the data exist in the FIFO ) ...
