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fpga pwm signal falling edge problem

Hi all,

 

I have a problem with my pwm signal. I generate pwm signal with NI 9475 on cRio.

pwm_fallingedge.jpg

If you have any idea please share with me.

 

Thanks!

 

gulyvz

 

code hereby enclosed.

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Hi gulyvz,

 

according to the manual the NI9475 is a sourcing DO module.

 

I have a problem…

What's the problem? Blurry images?

 

I guess the picture shows the voltage vs. time and you speak about the falling edges: is there any capacitor (or low pass) connected at the DO?

What did you connect to the module? Can you supply schematics?

 

Best regards,
GerdW


using LV2016/2019/2021 on Win10/11+cRIO, TestStand2016/2019
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Hi GerdW,

 

I have a problem with square signal falling edge. I want to generate square signal which duty cycle adjustable.

 

I hope it will be clear.

 

Thanks

gulyvz

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