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fpga- optimum PWM generation

 

Hello guys,

i'm desperate for help, i'm trying to implement a PID on FPGA and i think i'm almost there... since the output values of PID doesn't go as far as i want to (like tick values), i decide to relate them to obtain the values that i after send to PWM tick comparison to generate the PWM duty-cycle. I already am capable of view the values generated by PID varying from 0 ticks to 40M ticks, although i can see the values in my indicators and in a graph that i have on Host, when put them to be comparated my channel 1 goes high and my channel 2 goes low and never change. The strange thing is that the PWM out put didn't change but the PID values of OUT_I32 that i have in the same SCTL keeps on changing to compensate as drop or rise the voltage value. May the problem be the relate code that i'm doing?? or is it because i'm getting the values to the SCTL by a local variable?
I have attached the project code.
Please help or give me some idea.



Thanks in advance.
Best regards
Mário Silva

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Message 21 of 23
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Try breaking out the PWM generation into its own subVI and running that in simulation (in the project explorer, right-click the FPGA target, and choose Execute VI On -> Development Computer with Simulated IO).  Replace the outputs with indicators so you can see what it's doing; I also removed the PID On/Off and PWM A (On/Off) controls to simply further.  As far as I can tell your PWM generates a signal so long as the Overflow value is larger than the Duty Cycle value.  If the Overflow value is less than the duty cycle, the select on the right side of the timed loop always sets the shift register to 0, leading to the behavior you describe.  I have no idea what the purpose of the Overflow control is.

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Message 22 of 23
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Hi M_Silva,

 

can u post your PNG images of VI,s??,

i have previous LabVIEW.

 

 

Best Regards,

azy

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Message 23 of 23
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