fpga-hybrid for RIO, DMA FIFO

[Russ_in_Louisville]

Hi,

I have a hybrid code (which I cannot post here but will use the attached as an example) of a VI on the FPGA target that is just a group of digital inputs. The rest of the code is on the Real-Time target. I understand there needs to be a DMA FIFO to pass information from the FPGA to the Real-Time target so the Real-Time target can share that with the host.

This is a two part question.

1. Why wouldn't the VI that's on the FPGA target be included in the block diagram of the DMA FIFO VI, say in between FPGA Write.vi and FPGA Read.vi, or some other place in the VI that passes through the digital input readings to the RT Target & Host?

2. Also, the RT-Target will need to collect the readings from the VI on the FPGA. Will I just drag in the VI that's on the FPGA into the VI on the RT-Target that's performing the control in my control system, say in a while or time loop and does the VI from the FPGA target need some conditioning in the RT system control VI?

See the note in RT Main.vi --> Timed Loop "I/O Engine"

[nathand]

There are no DMA FIFOs in the linked project. All communication between the FPGA and host (RT) is done through front panel controls.

In this example, and in most LabVIEW FPGA applications, the FPGA VI runs continuously in parallel with the RT code. You can run an FPGA VI and wait for the FPGA to finish, bu that's uncommon and that's not what's being done here. You cannot drop the FPGA VI onto the host diagram and have it execute like a subVI. Instead, in the host code you start the FPGA VI running on the FPGA by using Open FPGA VI Reference. You use front panel items or DMA channels to exchange data between the host and FPGA.

In the example, FPGA Write reads values from shared variables and writes them to front panel controls on the FPGA. FPGA Read does the reverse (reads values from FPGA indicators and writes them to shared variables). Since the FPGA is running continously in the background, nothing is needed between the read and write.

[Tortu]

Greetings Russ_in_Louisville

You may find these online resources helpful in getting your questions cleared, in case you still have doubts after nathand’s answer, which is correct.

[Russ_in_Louisville]

I understand the example that was uploaded may not represent what is being asked and may confuse matters more than doing good. So forget about the example for now.

1. In my code, the RT Target needs to process data read by the inputs on the FPGA target for the control system to work. The main reason for using the FPGA is because of the high frequency of the input device.

2. There's complex code in my "FPGA Main.vi" to allow for the RIO to read from the input device. So it's not as straight forward as dragging and dropping the I/O on the FPGA target into the FPGA Read.vi and FPGA Write.vi block diagrams, at least I don't think so. I might be wrong.

3. I am assuming the RT Target will be the host so it will have the ability to run headless and the HMI will be only for monitoring and adjusting settings as required. However, I am fairly confident there needs to be a "pass-through" for the HMI to show performance.

So with that said, would I drop my "FPGA Main.vi" into FPGA Read.vi and FPGA Write.vi block diagrams? My "FPGA Main.vi" would have terminals assigned to it and dropped in, in lieu of I/O.

With this goal in mind, is my program a candidate for DMA FIFO? I've gotten this response to from our local user group. https://decibel.ni.com/content/message/69873#69873 

I was under the impression from the FPGA class that DMA FIFO needs to be included in most FPGA programming with RIO devices and communication with HMIs.

[nathand]

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Russ_in_Louisville wrote:

So with that said, would I drop my "FPGA Main.vi" into FPGA Read.vi and FPGA Write.vi block diagrams? My "FPGA Main.vi" would have terminals assigned to it and dropped in, in lieu of I/O.

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No. As I explained before, you cannot drop an FPGA VI into the block diagram of a host VI - that's not how it works. You need to load the FPGA image ("Open FPGA VI Reference") and run it. You can then exchange data between the host and the FPGA, which are running concurrently, using front panel elements and DMA FIFOs.

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@Russ_in_Louisville wrote:
 With this goal in mind, is my program a candidate for DMA FIFO? I've gotten this response to from our local user group. https://decibel.ni.com/content/message/69873#69873 

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A DMA FIFO is appropriate if you are pushing several pieces of data, of the same datatype, from the host to FPGA or vice versa, in a single burst and you cannot lose any of those data points. For example, let's say your FPGA implements some type of serial communication. Settings such as the baud rate would be a front panel element (a single value that does not change frequently), whereas the data would be transmitted through a DMA FIFO (it arrives or is sent in bursts and losing a character is problematic).

If your FPGA reads data at high speed and needs to pass all of it through to the host, then a DMA FIFO is appropriate.

If your FPGA reads data at high speed, computes some result, and the host only needs to know the most recent result, then you should use a front panel indicator.