fpga fifo

[m_ruet]

Hi,

i am using crio 9022 and chassis 9118. i am tring to implement DMA fifo. i have 36 temp channel and 24 analog channel. i have done all thing to implement fifo. i used 3 fifo. one for analog, one for temp and one for host to target. i run the fpga in the target and its working fine but i am building exe file for real time controller its is getting connection out. and if its getting connection its not working. before it was running with fpga input ouput node and it was working fine. i just want to switch in dma fifo. can some one plz help me about this. and i tried very simple program just for reading the fifo but its not building the exe file for crio.

regards,

Amin.

[Mellobuck]

Hello Amin,

I am trying to clarify the specific problem here. You said that the cRIO worked fine with the FPGA input output node. How fast was that reading data vs. how fast are you reading it now.

With FIFOs there is often an overflow error: the FPGA is putting data into the FIFO much faster than it is read out. This is typically solved by reading more points at a slower rate on the cRIO. Example: the FPGA puts 10 points into the FIFO 10,000 times a second, then the cRIO needs to either take 10,000 points 10 times a second, or 1000 at 100 times a second to match the input rate.

Finally, did you say there was a problem with builing and deploying the EXE? Can you build the FPGA bit file correctly? Can the RT program start the FPGA program and start the FIFO acquisition without error?

Is the error that the cRIO EXE does not build? If so, that is the first issue to address, what is the error message on an unsuccessful build?

Regards,

Mello

[m_ruet]

Hi,

i tried your option but it was also not working.  i did very simple program only just reading writing from and to instruments but my target to host fifos were working but host to target not. i am using three fifos in fpga interface mode. or may be my reading from fifo is not correct. i also increased my depth very high like 25000 elements in the host side when this was not working then i tried to generate less data in fpga side. that time it was running with host side loop after same time counter.

regards,

Amin.

[m_ruet]

Hi,

my fpga code is working in the target when i downloaded in the fpga and i ran it perfectly. sometimes exe file is generating but its running in real time but i

am not getting any datas....

regards,

amin.

[Topper_Harley]

Hi Amin,

please verify that both your real-time code and FPGA code is executing. The easiest way to do this is switching FPGA and USER LEDs on and off.

How Do I Access the User LEDs On My Compact FieldPoint or CompactRIO controller

http://digital.ni.com/public.nsf/allkb/6E8694E997B5FCB3862572CE00463067?OpenDocument

Once you know that your code is actually running, you can investigate further.

Reagards, Topper

[m_ruet]

Hi,

i followed your instruction but still i have some problems. now connection is robust i.e network connection and led for user and fpga are flashing when i am running this. but the main problem is i am not getting any data in real time host  side. i am getting empty array in CRIO side. The prgram is running fine just i am not getting data. on fpga side its showing data in indicator but not any value in RThost.

FPGA side:

Number of chanel=36

Time out=0

Loop rate 100 ms 

Dma size =1023

Two NI 9213 

RT side:

Number of element =36 i tried also more but same empty array.

time out= 5000 ms i tried with -1 and many others value but empty array.

Crio 9022.

loop rate =50 ms but it has less priority and higher priority loop has 100 ms loop rate.

i think, i am doing something sily do i need to check any other things. i am using labview 2010 sp1 and Ni rio 3.6 with ni scan engine 2011 jan. both side. please help me some one....

regards,

Amin 

[Topper_Harley]

Hi Amin,

it's good to hear that you made some progress and your RT and FPGA programs are running.

Please have a look at these documents:

Using DMA FIFO to Develop High-Speed Data Acquisition Applications for Reconfigurable I/O Devices

http://www.ni.com/white-paper/4534/en

Simple DMA FIFO Example for FPGA

https://decibel.ni.com/content/docs/DOC-9893

Check on the datatype of your FIFO. Try sending constant data via the FIFO before connecting AI.

Topper