fpga data persistence volatility

[JordanJMcBain]

I was just wondering about the persistence/volatility of the various memory methods after cycling power to LabVIEW FPGA Devices?  Is it possible to ensure that data persists after cycling power?

[nathand]

No. When you cycle power to the FPGA it is cleared. To persist data you need to write it to disk in the host application, then reload it after restarting the FPGA.

[JordanJMcBain]

Thank you for the quick response.  Are we certain that _none_ of the memory techniques have persistence after cycling power?

[nathand · Accepted solution]

There aren't that many memory techniques. You can store data on the FPGA either in logic gates, or in RAM. Both of those are volatile - they lose their contents when not powered. Some FPGA boards do have onboard non-volatile FLASH, but that is generally used to store a bitfile to be loaded on power-up. I do not know if it is possible for the FPGA to access the FLASH while running, but if it is you would need to write custom low-level (non-LabVIEW) code to do it, as there are no built-in functions that allow it.