fpga compilation problem (generating cores)

[iWINuFAIL]

Hello.  I am working in a lab trying to compile an FPGA for the cRIO 9074 module.  There are no erros when beginning the compilation, and it runs smoothly until it reaches the "generating cores" step.  At this point the following message repeats itself

All runtime messages will be recorded in
C:\NIFPGA\jobs\XR923g4_G4EhsMk\coregen.log
Saved CGP file for project 'coregen'.
Resolving generics for 'ReallyLongUniqueName_ReallyLongUniqueName'...
Applying external generics to 'ReallyLongUniqueName_ReallyLongUniqueName'...
Delivering associated files for 'ReallyLongUniqueName_ReallyLongUniqueName'...
Generating implementation netlist for
'ReallyLongUniqueName_ReallyLongUniqueName'...
Running synthesis for 'ReallyLongUniqueName_ReallyLongUniqueName'

This message repeats every 5 min or so for around 29 minutes, at which point the compiler stops, presenting the following error

ERROR:sim - Cannot rename dependency database for library "mult_gen_v11_0", file
   is
   "_cg/_dbg/ReallyLongUniqueName_ReallyLongUniqueName_xsd/mult_gen_v11_0/hdpdep
   s.ref", Temporary database file
   "C:\NIFPGA\jobs\I1wyNri_G4EhsMk\core_NiLvXipFloat32Add\tmp\_cg\_dbg\ReallyLon
   gUniqueName_ReallyLongUniqueName_xsd\mult_gen_v11_0\xil_95296_48" will
   remain.  System error message is:  File exists

ERROR:sim - Failed executing Tcl generator.
ERROR:sim - Failed to generate 'ReallyLongUniqueName_ReallyLongUniqueName'.
   Failed executing Tcl generator.
ERROR:sim:877 - Error found during execution of IP 'Floating-point v5.0'

I have included the xilinx log.  For good measure I compiled an older FPGA we have running on a different chassis and it ran just fine, so it's not a problem with xilinx (at least I don't think it is).  I have spent the better part of two days wrestling with this issue and have found no viable solutions.  Any and all help would be greatly appreciated.  Thanks!

Cheers,
David

[iWINuFAIL]

bump for help

[diabeticdaniel]

Check out this document from Xilinx. It may be caused by your antivirus not allowing access to the files that Xilinx needs to overwrite while compiling.

[iWINuFAIL]

Thanks but that doesn't appear to be the problem.  Firewall is disabled and the computer has no antivirus software.  I tried renaming the FPGA VI and trying again but that did not produce the dsired result.

[diabeticdaniel]

Sometimes starting over from scratch with a new project and new VI can resolve some of these weird errors. Try creating a new VI and just copying and pasting the code on your block diagram to the new VI and recompiling.