Great PDF guys. I just read through V 1.1 and found one mistake and would like to make one general suggestion.
In the table on page 81 it's written "Random read/write access to moderate amounts of memory (kilobytes) from up from two clock domain" for Primary use of BLock RAM Memory items. This text is a bit unclear.
In addition a general note. The difference / similarity between feedback nodes (with and without reset signal and initialisation) and discrete delays is mentioned in multiple places and seems a bit confusing. In one place it's written that discrete delays are much more efficient because they use SRLs but later it's alsow ritten than Feedback nodes without Initialisation or reset signal can ALSO use SRLs. I think this can be communicated a bit more clearly.
Other than that, really great document. Keep it up.
Shane
PS A lot of things touched on int he PDF could be illustrated with example code. The document really needs to be a lot more comprehensive ins ome regards but it's a more than welcome step in the right direction.
PPS Some up-to.date resource utilisation charts would be a really nice addition.
