[fpga] Faster communication between FPGA and real-time host

[WarWolf]

Hello everyone,

I got a NI FlexRIO (PXIe-7965R) FPGA card installed on a PXI chassis (PXIe-8135 embedded controller). I have a FPGA program running at 40 MHz, and I am using a real-time program to read a particular FPGA variable at regular intervals. I am not trying to stream the data. All I need is to get the latest value during every loop execution of the real-time program (hence, DMA FIFO is not a good option). I am aware that one can read the FPGA indicators in the host (real-time) program using FPGA Read/Write control function. I used this function to read a certain FPGA indicator variable, as shown in the screen shot. This RT program takes 100 micro seconds (10 kHz) to execute, which is not fast enough for my application.

Is there a faster method to read latest data from FPGA, or can the program shown in the screen shot be modified to reduce the RT loop time? Any help would be greatly appreciated.

[0utlaw]

Hello Imkumaran,

It appears that you've configured your timed loop to execute once every 100 mS, so it makes sense that that is how long it takes to execute- timed loops are used when reliable execution times are more important than throughput. 

If you need to read values as fast as possible, you should use a standard while loop rather than a Timed loop.

How fast do you want this to execute?  Does your RT code need to be deterministic?  Can you adjust the timed loop's duration?

Regards.

[WarWolf]

Hi Tom,

Thanks for your reply. I want my RT code to be deterministic. Eventually I'm planning to use the measurement I get from FPGA to run a PID control loop, so I got to use timed loop. I did reduce the timed loop's duration, but the code is not deterministic for any duration less than 100 micro seconds. I would like to run the code as fast as possible with determinism.

It is surprising that the FPGA read/write function is taking so much time (100 micro sec) to execute. I have real time programs performing complex tasks within 100 micro sec.

[nathand]

The best thing to do here is to put the PID control loop on the FPGA, where you will be able to execute it deterministically at a much higher rate.

[WarWolf]

That is true, but I have lot of other stuff running along with PID loop that cannot be implemented in FPGA. Hence, I have to transfer data from FPGA to real-time program.

Has anyone tried implementing FPGA-real time communication? if so what is the rate of the real-time loop in your program (my case its 100 micro sec for reading a single FPGA variable in RT)?

[dan_u]

I'm surprised it takes so long. We use DMA to transfer data between FPGA and RT up to 25kHz. Just reading from the FIFO on the RT takes approx. 8us, so that would theoretically allow RT loop rates up to ~100kHz.

Maybe you should give DMA a try, even though I also thought for single controls it's more efficient to use Read/Write Control.

[nathand]

You can transfer a lot of data in a hurry over a DMA FIFO, but you're trading bandwidth for latency. The DMA FIFO has high bandwidth so the average rate is very fast, however it's not ideal for transferring a single piece of data as you would need to do in a control application.

Have you looked at this thread?

I'm really curious - what process are you controlling that requires that the PID loop run so fast? Can your physical system actually respond that quickly?

If you do need the PID loop to run so fast and deterministically, moving it to the FPGA is the best way to go, even if it requires rethinking some of your architecture to separate parts of the loop.

[WarWolf]

dan_u,

I first tried using DMA FIFO, but found it to be inefficient for transferring single point data. Even with DMA FIFO, my rate was just 10 kHz (loop rate).The time taken by RT to just read the FIFO was around 40 us. I am very curious, and would like to know  how you are getting 8 us. I am attaching a screen shot of my RT program. It would be great if you can compare it your program and tell me where I have gone wrong. I appreciate your help.

P.S. FIFO_rms is the name of the FIFO, and I couldn't reduce its depth below 512.

[WarWolf]

nathan,

Thanks for pointing the relevent thread. I am trying to benchmark my FPGA in a similar fashion. I believe it will help me decide which method to use for data transfer.

My goal is to simultanously control 5 piezo based nano positioning stages. These stages typically have their resonance at ~10-50 kHz range. So, all I want is to operate just below the resonance around say ~10-20 kHz. My FPGA runs at 40 MHz which seems a bit overkill to me. Moreover 5 stages require  5 output and 5 feedback channels to control it, which my FPGA, at present, does not have.

[dan_u · Accepted solution]

You're talking from a RT target to an FPGA card sitting in the RT itself? If so, have you tried without the IP address of the target. See this thread to see why this could make a difference.