default (initial) value of feedback node when datatype is FPGA tickcount

[aetc]

Is the default (initial) value of feedback node when datatype is FPGA tickcount a 0 or the actual FPGA tickcount at the time the node is run?

[RavensFan]

I would say the default value is zero.  How would the feedback node know anything about a tickcount?

[aetc]

My understanding (and correct me if I'm wrong) was that the tickcount starts at 0 when the unit it powered up and using a base-clock frequency of 40MHz and the datatype of a U32 simply increments every 25ns until it has reached 2E32-1 (max value of a 32bit integer) at which point it 'wraps around' and starts back at 0. At any point afterwords during run time (for example the start of an FPGA program) the tick-count would be some value between 0 and 2E32-1.

The question was posed with this basic FPGA logic in mind (see attached). In the help file for the feedback node the default value, assuming it has not been initialized with something else, is the default value of the datatype - here U32, which would in fact be 0; however if it is initialized with the outut of the tick-count vi - is it still 0 or the tickcount at FPGA program startup?

[RavensFan]

Thanks for the picture as that helps clarify things.

The i terminal, according to the help, is Denotes that the "Feedback Node initializes on the first call of the VI. "

So the initial value of the feedback node when the VI is first called will be the value from the tick count function.  Which might be nearly zero if the FPGA just restarted.  (Maybe a few tick counts would have already passed.)

Now if you stop the VI and restart it, I'm think it will get whatever tick count is present coming out of the tick count node at that moment.  Or maybe it will be the last tick count it saw when the VI was stopped.  I'm not certain about the operation of the FPGA do know if you stop and restart this VI, if it is considered a new first call, or only a continuation of the past calls, particularly if this is behaving like a top level VI.  Also, I'm not sure whether the tick counter restarts at zero upon restarting the VI, or only when rebooting the FPGA.

I wish I could give you a definitive answer.  Your best bet would be to just code it up, try it out, and see what the results are.

Oh, by the way., a U32 for a 40 MHz clock rolls over about every 107 seconds.

[aetc]

Yup - got that same 'rollover' duration too - thanks