connect ouput to input virtual device

[ThijsBoeree]

Hi,

Can anyone telle me how to connect lets say analog out 0 to analog in 0 with a virtual device? On my work i have a USB-6211 but i want to test some code at home...

I know how to create a virtual device, but don't know how to " virtual wire it" 

Best regards,

Thijs

[Dennis_Knutson]

What is a virtual wire? What it's the data type of your DAQmx Read and Write? They can both be a waveform data type so the wiring should be simple.

[Dennis_Knutson]

Just realized you were asking about a write connected to a read and not block diagram wires. A simulated write does not output anything. You need physical hardware to output a physical signal. The simulated DAQmx Read is always the same and the DAQmx write is irrelevant.

[ThijsBoeree]

In my software i write a 2D double array to my USB analog output, and i have hardwired my USB-6211 ao0 to ai0 (real hardware, daq device) but now i want to simulate this with a virtual device (with NI-Max you can create virtual devices) but you're saying this isn't possible?

Regards,
Thijs

[Dennis_Knutson]

The simulated analog read returns a simulated sine wave and not your simulated signal that you pass to the simulated analog write.

[Michael_78]

If I want to simulate, I create a wrapper for the input and output functions and choose which vi to run, the daq or the simulate. This is an excellent use case of labview classes and dynamic dispatch but ot can be done without classes too. Michael

[ThijsBoeree]

Do you have an example?
Thijs

[Dennis_Knutson]

At its most basic, you could simply use a case statement. One case has the actual DAQmx Read and the other has your signal. The signal can be a constant that you captured with the actual hardware or the data you pass to the DAQmx Write.

[crossrulz]

The best way is to use a Conditional Diagram Disable structure.  This way you can make a project variable.  You then have two different cases in the CDDS, one for Simulated and one for not.  The best part of doing it this way is that the compiler only compiles the active case based on your project variable.