clock timing - digital output

[brentjustice]

Hello everyone!

I need to impliment hardware timing on a few digital output lines.  This is what I have so far:

I haven't taken an oscilloscope to it yet, but I'm fairly certain that this is working.  Please note that in this example, I am using a PCI-6115.  I have 2 questions:

1) Does what I'm doing look reasonable at a quick glance?

2) I'm a little mistified by the clock source input to the sample clock function.  The docuemntation that I've read just further confuses me.  I understand that the clock is what dictates the hardware timing sequence.  I cannot understand how to properly select the appropriate clock source.  More specifically, in the example above, I only got the program to work when I selected "20MHzTimebase".  What is this? Why did this work?

when I attempt to select "Dev1/do/SampleClock", I get the following error: "An attempt has been made to perform a route when the source and the destination are the same terminal."

When I attempt to select either "Dev1/PFI0" or "DEV1/RTSI0", I get a timeout error from the wait_until_done.vi --> it doesn't appear that the waveforms are executed.

What does PFI and RTSI stand for, and why do they appear as options when selecting a clock source?  Furthermore, why did they not work as a clock source?

I would be very grateful to anyone who could clear things up for me a bit.  Thank you!

[Dennis_Knutson · Accepted solution]

Have you read the manual http://digital.ni.com/manuals.nsf/websearch/01C075FB9478F94A8625786A007435BA? The definition of PF and RTSI are in there. They are for using external clock signals. You have a choice of using the internal analog output/input clocks (the 20MHz) or external clocks. If you don't connect the PF or RTSI bus to anything, you have no clock so no data will be output. Selecting DO as source does not work because it is not a source. You provide a source for it.

[John_P1]

It looks reasonable at first glance except for the clock source.

In the image you have posted, the 20 MHz timebase is used as the sample clock directly (well the route isn't direct, it actually uses one of the counters...).  It probably isn't what you really want to do.

Instead, you should either:

1)  Leave the clock source unwired to use the internal clock (you can also select "OnboardClock" if you wish).

2)  Specify another terminal if you want to use an external sample clock.

The Programmable Function Interface (PFI) and the Real-Time System Integration (RTSI) lines can both be used to route timing / triggering signals to / from the 6115.  The PFI lines are on the 68 pin connector, whereas the RTSI lines are available via a ribbon cable that can be used to connect multiple cards together that are in the same PC.

When you specified a PFI line as the sample clock source, there was no clock on the PFI line you chose so the data was not generated.

Best Regards,

[brentjustice]

John, thank you for the response.  This is super helpful.

I left the clock source unwired, but I then got the following error: "External sample clock source must be specified for this application."

I think that this simply means that these specific digital output channels on my PCI-6115 require an external clock source and do not have an internal clock source option available.

However, I also have an NI USB-6343.  According to the documentation, this DAQ has: "48 digital I/O lines (32 hardware-timed up to 1 MHz)".  If I'm understanding things correctly, I would potentially be able to leave the clock source unwired for these digital output lines --> this would result in the DO using their internal clock.  Does this reasoning seem correct?

Last question: For the example code that I have shared, I was able to use 1 clock for dictating the execution of 3 digital waveform digital outputs at the same time.  Does this simply mean that the digital output lines are sharing this same clock line?  How many digital output lines can share a single clock line?  And while the NI USB-6343 has 48 DIO lines, why does the documentaton suggest that only 32 can be hardware timed?

Thanks again for your helpfulness.  Things are slowly starting to make sense

[John_P1]

Oh sorry... yes the 6115 supports hardware timing but you must provide the clock from another source.  You can generate the clock signal using ctr0 and route it internally if you wish (like in this example, see here for the subVI).

The 6343 can generate its own digital output sample clock like you have mentioned.

All of your hardware-timed digital output lines need to be in the same task and will share the same clock.  So on the 6115, all 8 digital lines can be used in a single hardware-timed output task.  On the 6343, only the 32 lines on port 0 support hardware-timed digital output (they must also be in the same task and will share a common clock as well).  The remaining 16 digital I/O lines on the 6343 can be used as PFI lines or as software-timed digital I/O.

Best Regards,