cRIO external acquisition clock

[edf]

Hello, I'm attempting to translate some existing LabVIEW programming over to a cRIO device to increase speed with the FPGA.

Currently, we have a number of cDAQ modules in a USB crate, and a PC handling all the code and anlysis, but it gets a little bogged down with a high acquision rate and lots of channels. The acquisition clock is an external signal generator which is locked to a number of other sig-gens. It is crucial that the acquisition is synchronised to these other sig-gens for our application (precision phase measurement).

With the cRIO device though, I can see no way to supply an external clock, or synchronise the FPGA clock to the signal generators. I'm fairly new to the FPGA and RT modules, so perhaps I'm missing somethign simple? I found a KB article and some old posts on this topic, but they only seem to apply to PXI systems and my cRIO device is missing the options described.

The only way I have currently thoguht of to do it would be to use a DIO module and somehow syncronise the acquisition loop to a DI signal in code, but that doens't seem like a trivial task. Any suggestions appreciated! Thank you.

Cheers,

Ewan.

[Robert.L]

Hi Ewan

There is an example which uses the DSA module to synchronize multiple chassis.

Using the CRIO in FPGA it would be possible to use a digital input as a trigger and use a single cycle time loop to govern exactly when the device samples.  In FPGA you are governed by the speed of the internal clock. This would give deterministic acquisition.

http://zone.ni.com/devzone/cda/epd/p/id/6146

http://zone.ni.com/reference/en-XX/help/371599E-01/lvfpgaconcepts/external_clocks/