05-08-2010 11:50 AM
05-10-2010 10:51 AM
Your approach seems reasonable. One thing I would warn you about is that it can be somewhat tricky to multiplex the slow and high speed data together. It is definitely feasible, but it just requires quite a bit of work to implement.
You might consider doing the slow speed data with front panel objects to make your life easier. Although you can't use the scan engine, you can use a similar architecture for synchronizing the data. You can find out more about how the scan engine handles synchronization here: http://zone.ni.com/devzone/cda/tut/p/id/7693
Make sure to use some handshaking for the CAN messages so that you don't miss messages or send them twice.
Systems Engineer - Data Logging
05-10-2010 12:01 PM
Hi Ryan. Thanks for your answer. The number of slow channels will be higher than 40. Do you think I could have problems with front panel objects? One of the scenarios is composed by two CAN modules (NI 9853) and modules of other types (analog input and output, digital input and output).
05-10-2010 01:53 PM
Assuming that most of your slow updates happen at one or two speeds, you should be able to package the data to reduce the FPGA footprint. For example, you can pack all of your digital channels into a few U32s. I'd suggest compiling on your intended target before locking your hardware choice in though, the CAN modules can take quite a bit of FPGA real estate.