We have a cRIO Profibus module installed in a cRIO-9024 chassis, and are experiencing difficulties during the FPGA build process. The build goes fine when the project is configured for the Profibus module to be in Slot 1, but fails with Code Generation Errors when the project is configured for Slot 7. I have created a very simplified pair of projects (attached) that illustrate the problem.
The error messages are "HDL code generation error occurred" and "Terminal(s) requiring constant input wired to non-constant source(s)". A screenshot is included the attachment.
Commenting out the second subVI "CS_cRIO_PBM[7]FPGA_SPI_ReadWrite.vi" in Profibus_Slot7.vi allows the FPGA code to build without errors. Tried wiring constants to the subVI inputs, and other variations, but still the build failed.
I am aware that the documentation for the Profibus module recommends installation in Slot 1, but our customer requires us to install it in Slot 7.
Does anyone have an understanding of the Code Generation Errors that I am receiving?
