Hello.
I am attaching the whole project this time. I hope that someone will undestand what am I doing wrong.
I am using the cRIO 9082 in windows embedded configuration and the module I am trying to work with is the NI 9264.
I also have one question. The NI 9264 can give me up to 25 kSamples/Second. How does LabVIEW FPGA knows that the module cannot be updated every time the loop tries to update it? If for example I have a loop to be executed every 100 ticks, my module is not so fast, it cannot be updated at this rate.
In the first post, I attached a picture of my first vi's where the loop did not have a time delay. Could this work?
In this post, the vi that is handling the module update, is running a 1700 cycles delay loop (40MHz to 25 kSamples/Second = 1600) but the results are terrible, worst even from the first vi.
Any help?
Thanks,
Vasileios.