cRIO-9024 + NI 9113 Chassis + NI 9881 (CANopen) FPGA Compile Problem

[batuypn]

Hello,

I am started to learn Labview and i want to communicate with CANopen (9881) module in FPGA interface, but there is a problem.

Normally (without NI 9881),  i can compile and run a VI file with FPGA interface, BUT after adding 9881 (in slot1) to chassis (9113) i cannot compile any VI file (even same VI file) with compile worker. Even if i delete the Mod1(Slot1, NI 9881) from the project, i can compile the VI file.

I need to compile bit file in order to use CANopen library, but i could not find the problem.

Can anybody help me? Thank you.

The error is below:

...

 Parsing entity <CcMuxSLN>.
Parsing architecture <RTL> of entity <ccmuxsln>.
ERROR:HDLCompiler:849 - "D:\NIFPGA\jobs\g8Q6537_ibm705i\CcMuxSLN.vhd" Line 794: Unexpected EOF.
VHDL file D:\NIFPGA\jobs\g8Q6537_ibm705i\CcMuxSLN.vhd ignored due to errors

[Aix-La-Chapelle]

Hi batuypn,

What version of LabVIEW are you using?  

Are you using the NI-Industrial Communications for CANopen driver or the CANopen Library?  For use with the 9881 you must be using the NI-Industrial Communications for CANopen driver, the latest versions is 1.0.3.  The CANopen Library is used for Series 2 NI-CAN devices, and has been replaced by the NI-Industrial Communications for CANopen driver.

Can you post screenshots of the failed compilation?  Can you post the Xilinx Log produced by the failed compilation?

How large is your FPGA code?  The 9881 adds a large portion of FPGA code in the background, so if you were close to using all your resources previously, it may have pushed you over the edge in resource utilization.  Additionally, are you using any DMA FIFOs?  Are you in Hybrid mode or FPGA mode?  Hybrid mode by itself uses 2 DMA FIFO channels, and the 9881 will use 1.  This means on the 9113 you will not have any more DMA FIFOs available to use, and could also cause a compilation failure.

Thanks!

[batuypn]

Hi Matt,

Sorry for late response.

I am using LabView 2013 and NI-Industrial Communications for CANopen 1.0.3. I am not using any DMA FIFOs and my chassis is in the FPGA interface.

I followed the steps in the "Labview/examples/NI-Industrial Communications for CANopen/cRIO/CANopen_cRIO_FPGA_Dummy" instructions to create my project, and my FPGA code is empty to create bit files as written in the instructions. But as i wrote before, .vi file cannot be compiled.

Screenshot of error and the log file are attached. I am also attaching the .vi file which contains instructions that i followed. 

Thank you.

[BoKnows]

Do you have access to the cloud compile?  If so, have you tried running the compile there and see the same error?

If not, are you currently under the SSP?  If so, I'd like to use the cloud compile as a troubleshooting step to see if the error exists in both locations or if it is local to your machine.  Another way we can test this is to try to install the software and drivers on another machine and see if the problem still exists.

Here is information about the cloud compiler: http://www.ni.com/white-paper/52328/en/

[batuypn]

I've just tried cloud compile, and same error 

[Aix-La-Chapelle]

Hi batuypn,

I took a look at your Xilinx Log and found an error that I have seen in the past.  Typically this error pops up on Virtual Machines.  Are you currently using a Virtual Machine?  

[batuypn]

Sorry Matt, i am not using Virtual Machine

[Aix-La-Chapelle]

Hi batuypn,

Hm...that goes against what we have seen in the past.

Could you provide a MAX technical report of your computer?

I'm sorry, I may have missed this, but has this worked before? Do you have another computer that you can move this project over to? 

Thanks!

[Aix-La-Chapelle]

Hi batuypn,

Is there any update?

Thanks!

[batuypn · Accepted solution]

Hi Matt,

I uninstalled everything about LabVIEW and reinstalled it, i didnt do any update, for now the problem solved. It compiles the bit file. 

Thank you.