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cRIO 9014 frontpanel access causes high CPU load

Hello,

 

we have a problem with a cRIO 9014. We have a project that causes very high CPU load due to fast frontpanel accesses with LV2014. With LV2012 it is no problem.

 

To reproduce it: Create a single object on the FPGA frontpanel on a cRIO 9014 with LV2014 an compile it. Then create a host vi on RT with an adjustable looptiming and an access to the single object on the FPGA FP with Looptiming equal or less then 2ms. The CPU should be @99,9%. Why? What is the Problem? Why is it no problem with LV2012?

 

Any Ideas?

 

Thanks,

Wanja

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A 400MHz cRIO like yours may have met its limit.

This Performance Benchmark white paper shows a cRIO 9074 reaching 97% processor use at 500Hz (2ms period).

 

I'm not sure why your 2012 would work any differently. Do you have a CPU % usage that you've seen from that deployment? Are you able to pull a signal through the FPGA to make sure you're getting actual values in?

Cheers


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Hi Wanja,

 

James is right, your cRIO is a pretty old one and the loop times could be close to the limit of the CPU power.

You wrote "With LV2012 it is no problem.". Could you please specify the CPU load in this scenario. "no problem" is not a countable unit.

How do you run the RT.vi (btw if you talk about "Host" it normally means in runs on the (Windows) computer)? Do you run it interactively (open RT.vi on the Host -> click Run -> see the deployment to the cRIO), so you really "see" the RT.vi FP on your host computer? If so that is only meant for rapid prototyping and not for running an efficient applications.

One hint for future help: Please provide a sample project so everybody can see what you really tested.

 

Best regards,

Christoph

Staff Applications Engineer
National Instruments
Certified LabVIEW Developer (CLD), Certified LabVIEW Embedded Systems Developer (CLED)


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Thanks for your answers. We had the same project with LV2012 running on the cRIO9014 for a long time with no problems on the CPU load. Just in the near past there are problems. Our first thought was that it might be something with the newer LV versions, because we converted the project to 2014. But we come to the conclusion that it must be an other change that causes the high load.

 

The problem is a mix of high processor load and getting higher times on FPGA frontpanel accesses. The higher the CPU load is, the longer it takes to access FP elements. We have in the project a 5ms timed loop in RT with a CPU Load >80%. The FP accesses in this loop takes between 5-20ms. But I read here http://zone.ni.com/reference/en-XX/help/371599H-01/lvfpgaconcepts/pfi_data_transfer/ that high CPU load influences the time on accessing the FPGA FP. When I slow the loop time down for example to 10ms the access time gets more fixt to 5-10ms. So I come to the conclusion that you are right, that it is the limit of the cRIO. We will de-stress the CPU or take a newer cRIO with more power.

 

Btw - we ran the tests with deployed rt in autostart on the cRIO and viewed the CPU load with the NI-DSM. With "host" was the RT Host vi meant.

 

Best regards,

Wanja

 

 

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Hi Wanja,

 

you are welcome! Just let me know if any questions come up.

BTW: If you want to lower CPU load perhaps try DMA FIFO transfer if applicable since DMA transfer generally uses less CPU.

 

Best regards,

Christoph

Staff Applications Engineer
National Instruments
Certified LabVIEW Developer (CLD), Certified LabVIEW Embedded Systems Developer (CLED)


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