asynchronous I/O with PCIe-6535e and DAQ-mx

[Blah!]

Hi Folks:

  I'm trying to explicitly set and use either async or sync I/O using a PCIe-6535e DIO card with DAQ-mx. Nowhere in the DAQ-mx vi's can I find the means of setting either async or sync I/O. Does anyone know of a explicit vi citation say from the examples that I've missed where this is discussed and or set.

  Also, assuming I learn how to set the ack/write mode for the card, who sets the functionality and strobing of the PFI pin that will act as my data out/ data in flag? I can see in the manual that things like pulse width, delay etc are settable, but how do I set them? Or do I have to declare another channel with DAQ-mx and manually control those myself. I tried this, with no real success.

  As an example it would be really helpful to do this.

PFx pin _________-----------___________

line0:7   XXXXXX(  0xe7          )xxxxxxxxxxxx

For data out from the card.

and

line0:7  xxxxxxxxxxxx( 0xCA  )xxxxxxxxxxxxx

PFx pin ___________-----_______________

For data to the car. In this case I would strobe the PFx in from my FPGA.

I'm a bit confused as DAQ-mx does not seem to give me the control I need to set the I/O mode, and I cant find any explicit

mention as to who, or how to properly sync the functionality of the PFI pins with my data from within my vi.

Thanks.

Andrew

[ChacAttack]

Hello Andrew,

Have you had a chance to look at some of the shipping examples that come with DAQmx? If you open up LabVIEW and browse the examples, you can see how synchronization works with x-series devices (specifically Analog Input- Synchronization.vi). There are also some very helpful counter examples that you may find informative.

Here is a very helpful white paper about Timing and Synchronization.

After you review the white paper and look over the examples, feel free to post follow up questions. Thank you very much and have a great day!

[Blah!]

Hi Josh:

   Thanks a lot for those reading materials. They were meaty. So it seems the output style my application calls for is either "Sample Clock" or Handshaking Burst (export clock). Both pass data to the ports. I'll point to this vi as a working example....

https://decibel.ni.com/content/docs/DOC-12404

But it's still not what I need. I also need a pulse to (at this point, any pin) to mark to my application that data is ready to be be taken. I need a data ready pulse. I tried exporting the clock to one of the PFI pins, and I'm informed that thre is no routing from the counter output to ANY pin. I swept them all. Same with Burst (export clock) data flows but I have no ability to trigger a pin to pulse with the valid data, let alone during the period that the data is valid. Only 8255 mode seems to offer a solution where I can route signals in or out of my PCIe-6535b but that requires my application to actively request data from my National Instruments card. I'm trying to imput data into a latch, I need the PCIe-6535b to signal my external latches to accept data. My FPGA logic takes it from there.

Am I correct is understanding that the PCIe-6535e us unable to export any kind of data ready pulse corrilated with the data it outputs? What am I missing? If so, can you suggest a National Instruments DIO card that is capable if routing a pulse corrilated with stable port data? I have tried to generate one myself, but they have come out sloppy, with double pulses at the end and beginning of loops, and I seem to lack the ability to set pulse position and pulse width with respect to each word of data.

Thanks

Andrew

[ChacAttack]

Hello Andrew, 

I believe that I understand your application and what you are hoping to achieve with your device. I will look into how you can go about this. I have found some helpful links about the bidirectional capabilities of the PCIe-6535:

http://www.ni.com/example/30285/en/

Based on this, you may want to consider a PXI-655x devices:

http://www.ni.com/datasheet/pdf/en/ds-142

They are a substantial price jump, but I am not sure if there is a software based approach for your application. I will look into if further, but in the meantime, I want to suggest that you post this question on the Digital IO page. More often than not, our PSE's and other customers with experience using this device will be happy to help as well.

[Blah!]

Hi Josh:

   Thanks for staying with me. 🙂 One thing given that reading you sent me (Funny I came across it about 20 min before you replied to my post.) I'm not changing IO directions on a per read basis. I need to send a handful of bytes to my 'command parser'. The commands do things like set up the integration time on CCD camera and then command the shutter to open or not for that integration time. During the many 10's of seconds of image integration, I then change direction on the DIO ports to input. Where upon I receive a deluge of a few 100 Meg of raw image data.

  Changing IO direction is not my problem, it's centering a data valid flag while my output data is stable. I'm simply transferring data to a data latch on an FPGA, however it requires a pulse while the data is stable. It seems the fact that the PCIe-6535b has no internal counters is what's biting me. I'm trying to find a way to do the timing on the CPU of the computer to compute the pulse, or to try and roll thru an array with a for-loop. I tried this before, but it was pretty sloppy on the output. It seemed that the process of presenting the data on the output ports was running in parallel with the process that cycled thru the array of 'pulse data'. And the pulse was sometimes sliding into the previous or next data value time slot. It seemed as if I did not have clear control over when loops would execute. I even tried nested for loops, and still had similar problems. Is there a way in DAQ-mx to ensure one process has completed before starting another process? If I had that kind of control, I think the process of rolling thru an array of data to one of the PFI pins would work. I'd have one process presenting data on a port, then once that process is done, I'd roll thru the pulse array on the PFI line, then roll thru the next data value. However I need a means of making sure that those execute in a process by which no two processes are running at the same time, as it seems is happening.

Thanks.

Andrew

[ChacAttack]

Andrew,

If you are talking about verifying is a specific DAQmx task is complete, you can use a property node to read if the task is done. If you would like to post and/or send me the code you have built, I can take a look at that. Getting a visual of your data flow can help me better assist you.

I will talk to our Vision and FPGA team to see if we can come up with a solution for you.

In the meantime, have you checked out this FPGA Vision white paper?

[Blah! · Accepted solution]

Hi Josh:

    After talking with our academic technical help rep, he suggested I oversample the data and embed the pulse in the data. I did a little twist on the idea and I've attached a test vi I did. This creates just what I need. It'll work. I'd def like other options, but this is good enough for now. If I had a FPGA heck I could move the world, and I would not have to do kludgy code like what I've attached. I'd def be interested in hearing what other solutions you or someone else might come up with.

Thank You.

Andrew

[ChacAttack]

Hi Andrew,

Thank you for posting the solution that satisfied your inquiry. I'm happy that it worked out. Good luck with the rest of your project!