advice on finishing touches for circuit.

[labnoob]

hi, my code for my power quality monitoring project is almost finsihed i think. please disregard the fact that the even harmonic voltages arent wired yet, just havent got round to it. any way, the code is basically detecitng phenomenas. but i have a couple of question son how to tweak a few things.

1. as yo can see i have just added in a zero crossing ptbypt vi in the hope to somehow use it so i only log 10 full cyles. previously if i wanted to log 10 cyles, i could sample at 1000 and read 1000, but this is not very efficient as it doesn not capture the complet waves at start or end. advice would be much appreciated on how to tackle this, i had an idea i could somehow count 10 corssings from plus to minus then pause for 10 seconds, then repeat in a loop. how could i accomplish this? or if anyone has a better idea?

2. when a phenomena occurs, e.g. harmonic voltages exceeding the level by the standsads i show this my display an illuminated LED and also the leve its at. how then could i log this in a report or table so it shows the time and level of the event. but not report anything when its ok?

think thats all my questions for now. i have attached my code in case anyone is able to give advice.

thanks . 🙂

[labnoob]

also, can you tunnel info out of a while loop while its running? i tried but tro no avail.

[labnoob]

anyone?!

[altenbach]

Well, I see a few broken wires, so it is definitely not finished. 😉 I only briefly glanced at your code, and there are some glaring issues that should be addressed. (I currently don't have DaqMX installed, so I cannot comment on the DAQ part.)

Sequence frame 0

1. You have set your collector to a max of 2147483647 samples (!!!). You cannot be serious!. This will guarantee that you run into memory problems if you run this for a while.
2. Set the control for the delay to U32, no need ot coerce.
3. ...

Sequence frame 1

1. The code of the entire big loop needs to go inside the TRUE case of the small case structure. It makes absolutely no sense to execute all that code if no file is read, right?
2.  You should eliminate the while loop, because it simply operates on the same data over and over again. No need to keep it spinning.
3. You should make the boolean and DBL indicators into arrays, it would really simplify the diagram.

Front panel

1. Your front panel is too wide, make it fit a normal screen. You could use a tab structure for the two parts.

Block Diagram

1. Get rid of that big sequence structure and use a state machine architecture instead.

The above comments should keep you busy for a few minutes. 😉 Let me know if anything is not clear.

Of course we also need to know the purpose of this VI. Right now it is marginally sufficient as a "proof of concept" to interact with your hardware and for your personal use. If this is to be distributed or used by others, it need quite a bit more work.

[RM2]

Can you post that vi in 7.0 format?

[MarkLe]

Hi lanoob,

I've had a go at re-writing your vi in the state machine architecture that Altenbach suggested - this structure will allow you far greater flexibility in programming your application, allowing you to add functions and change order of execution easily (the code I've attached is only partially finished, but should give you an idea of how to continue).

If you haven't seen one of these before, it's one main while loop, with a case structure inside it. The piece of code which is exectued in each iteration of the loop is controlled by an enumerated type wired into a shift register, so you can directly alter the transition from one case to another using enumerated constants. You can add or remove cases by right clicking on one of the constants and selecting Open Type Def. From there you can edit the cases available, apply changes from the file menu, and re-save the control.

Regarding your other questions, you can't directly wire out of a loop while it is executing, this is part of the idea behind dataflow programming. If you want to communicate between loops while running, you will need to use a variable structure, usually within one VI, a local variable. You can, however, also write your code around structures such as Producer/Consumer loops (these can be found under the included VI templates).

If you want to log events once a certain condition has been met, include a case which writes to file, and call it as the next case every time the condition is met in the current case of your VI.

I hope this helps to get you going.

Mark

Applications Engineer

National Instruments

PS - I've also added a tab control, as already suggested, to organise your front panel somewhat.

[labnoob]

thankyou for your time. could you possibly resave for version 7.1. its not letting me open it!


thanks again.

[MarkLe]

Hey lanoob,

Sorry for posting in version 8, here's a copy I (hope) is saved properly for 7.1

Best wishes,

Mark

[GerdW]

Hello Mark,

my LV7.1 says: "load error 24: vi is broken and has no block diagram" for the big vi (1.3MB is not common, atleast not for me)...

[labnoob]

im not entirely sure thats working for me, im getting an eror when trying to open it!

you sound like the man to ask for ths other problem im having! if you can spare  2mins i'd appreciatte you looking at this code and maybe you can tell me why its not working propely, and perhaps sugest a fix?

basically, i need to collect the signals from the bit in the case structure after every aquisition. when i feed them to the collector in that other while loop, its almost as if its just collecting the very first iteration. as the collector appears to continue but the other part seems to stop. can you see what im trying to do? or am i making no sense!!


how could i fix this, im ready for horsing this computer out the window 😞

cheers.

LN