01-11-2016 03:53 AM
Hi,
In my application I am acquiring samples at the rate of 1 MS/s and transmitting the data values along with the timestamp using a FPGA to RT DMA FIFO . I need to decimate the acquired sample values by a decimation factor of 15 prior to the transmission . Is there a Xilinx IP which does this, and in such cases could you please provide a link containing the documentation process for making adjustments in the settings?
Thanks.
01-11-2016 06:26 AM - edited 01-11-2016 06:27 AM
If you don't need to average/filter data you can just use a counter. When it reaches the desired decimation write the value to the FIFO and reset the counter to 0.
01-12-2016 02:05 AM
HI,
I did a quick google search on 'Xilinx IP decimation'. a few of the filters seem to have a decimation option:
http://www.xilinx.com/support/documentation/ip_documentation/fir_compiler_ds534.pdf
01-12-2016 08:49 AM
Hi,
Thanks a lot . I will try this and get back to you asap.
Thanks once again.
01-12-2016 08:52 AM
I dont need to use a FIR filter for this just decimate by a factor of 15, not sure if I can use decimate option on the cRIO controller rather than doing it on the FPGA without using a Xilinx IP any suggestions on this. would be really helpful.
Thanks.
01-12-2016 09:15 AM
As dan_u mentioned, if you don't need filtering but purely decimation, there is no need for Xilinx IP. Simply read from the I/O in a loop but only write every 15th element to the DMA channel. If that is not sufficient for your use case, we will need more information, preferably an example, of what you are trying to accomplish. Cheers!
01-12-2016 10:41 AM
Hi,
Thanks a lot I will try that solution and get back to you asap.
Thanks.