Writing multiple elements to a FPGA to RT DMA FIFO

[James_McN]

Hi Harss,

So I would split it slightly differently.

I would have 1 loop that only reads from the local FIFO and the ADC then a seperate loop that does the processing to find valid chunks and this could then still have the DMA FIFO since it doesn't matter so much if it is slow. So we have:

Loop 1 - Capture time and trigger ADC

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FIFO 1 - Timestamp (as you have already)

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Loop 2 - Capture Matching timestamp and ADC sample

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FIFO 2 - Timestamp and ADC Sample

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Loop 3 - Trigger processing and DMA Transfer (this could be split again but I expect less gains)

This design is focused on making sure that Loop 2 ALWAYS runs at 1uS interval so we get every sample buffered for processing.

So for FIFO 2, when it is an internal FIFO you can use a custom type definition for the FIFO so this could be a cluster of the timestamp values and the ADC sample so it is easy to read. We know that loop 3 could stop processing values from the FIFO for around 2.6uS so we need it to be big enough to support that. This is actually only 2 samples but I would maybe set to 50 since you should have plenty of resources available anyway. This could be an LUT implementation.

This way when loop 3 pauses to send the 32 sample packets, loop 2 still runs as fast but starts to fill FIFO2. You need to make sure when Loop 3 isn't queuing data it is fast enough to then empty any data from the buffer before the next trigger point (so this needs to run faster than 1uS in this mode, which it already has to in the same loop).

[Harss]

Hi James,

Thanks a lot for the elaborate,clear explanation, the implementation on the FPGA is now clear to me.

I got an opportunity today to log the data points obtained from the FPGA onto the cRIO and it seems they are correct and I do not loose any data points so I guess the issue is with the transportation of these values from the cRIO onto the PC.

Here's a list of things I tried to implement on the cRIO

1:Used Network Stream Write Single Element inside the For loop, it caused the number of elements remining in the FPGA to RT FIFO to increase continously causing the FPGA  to RT FIFO to Time Out

2:Used the Queue to transport the cluster of Sample Values and Timestamps to another parallel While loop which solely uses Network Streams to transport these values to the host PC but this logged very few data points onto the PC and a lot of them were indeed missing(Probably could be due to improper wiring of the Network Streams function inside the loops not sure)

3:Used the Network Stream Write Single element function outside the For loop to write the entire cluster of 2D array outside the For loop, this too allowed me to log very few data points (Probably could be due to improper wiring of the Network Streams function inside the loops not sure) 

4: Tried writting the TDMS file inside the For loop could log most of the data points on the cRIO , but the number of elements remaining in the FPGA to RT DMA FIFO keeps on increasing eventually causing the FIFO to Time Out.

I really do not understand this and would really appreciate your help/suggestions on this implementation. I have attached the snapshot of the VI on the RT

Thanks once again.

[Harss]

Hi James,

I have not been able to work on cRIO for  while. However, I really appreciate your time and efforts for helping me understand the issue. 🙂

Thanks once again.