Writing multiple elements to a FPGA to RT DMA FIFO

[Harss]

Hi,

Thanks a lot for clearing my doubt.

I just wanted to check if my understanding is correct.

1: Place the Create Writer Stream Endpoint function outside the While loop.

2:Wire the error wire at the output of the Create Writer Stream Endpoint function to the input terminals of the 'Wait on IRQ block on the RT'

3:The error wire at the output of the Create Writer Stream Endpoint function is also wired to the Network Stream Write input terminals.

To summarize I have attached the modified image of the VI on the RT. Could you please help me understand if this is the right way.

Thanks once again.

[crossrulz]

I would actually go as far as to have the error output of the Sample Period read wired to the error input of the Create Writer Stream Endpoint.  I would just have the one chain of errors

[Harss]

Hi,

Thanks a lot for your feedback.

I have rewired the VI on the RT . Could you please check if this is the right way to do it.

Thanks.

[crossrulz]

The error wires look correct.  But you are mixing up your references.

[Harss]

Hi,

The mixing of references is I guess the wiring at the output of the Create Network Stream Writer End Point function. I think the wiring of reference out of the Create Network Stream Writer Endpoint to the  input of the Wait on IRQ block could be correct , but maybe the wiring of the reference Out of the Create Network Stream Writer Endpoint to the Network Stream Writer inside the For loop is incorrect and needs to be corrected, if that is the case then maybe I should wire the output Error terminals and the Reference Out of the FPGA to RT FIFO.Read block to the input of the Network Stream Writer  to eliminate the mix up?

I have attached the snapshot with the modifications. Could you please provide your feedback on it?

Thanks.

[crossrulz]

The FPGA reference can only go to FPGA functions.  The Network Stream reference can only go to Network Stream functions.  They are references to two completely different interfaces and you will have compile errors when you try to mix the two.

[Harss]

Hi,

I implemented the VI on the cRIO with the necessary changes but the FPGA to RT FIFO still times out . I later tried to read the entire 2D array by using autoindexing outside For loop . Hence, I tried to read to entire 96000 elements which was flushed from the FPGA to RT FIFO . The FPGA to RT FIFO did not time out now.

I will try to explain the issue I am currently facing

1:My test signal is a 20 Khz sinusoidal signal generated using an arbitrary waveform generator.

2:After applying the processing steps I try to acquire only the positive half cycle of the sinusoidal signal

Since I am sampling at 1 MS/s, therefore

I get 1000000 samples in one second , which means I should be able to reconstruct one cycle of 20 Khz signal in 1000000/20000 = 50 samples . Hence, the positive half cycle of the signal should be reconstructed in 25 samples.

After, I log the data points on the PC I see that sometimes only 17 or 18 data points allows me to reconstruct a single positive cycle of the  sinusoidal signal successfully because I think I may be missing out on certain samples or the data rate is reducing. I dont feel there is an issue in the FPGA logic , because when I used the Network Stream writer inside the For loop and logged the points the FPGA to RT FIFO did time out , but the data points were as expected without any loss in data rate. I think my current implementation on the cRIO is causing some issue.

It would be really helpful if you could suggest the right way of transporting data points without any loss in the data rate.

Please Note: On the RT I flush 96000 elements from the FIFO I use a Reshape to 2D array function which gives me 1000 rows with each row comprising of 96 elements I reconstruct the timestamps here and I get 32 sample values and 32 timestamps in a single iteration of the For loop. So my 2D array containing autoindexing  of the For  loop would allow me to read 64000 elements , if I consider using Network Streams to write the entire 2D array like in the current case.

Please find attached my VI on the RT . Any help/suggestions would be really appreciated.

Thanks.

[Harss]

Hi,

I checked this issue and  feel there is some data loss . I am not actually able to troubleshoot this. Could you please suggest the best possible way to transport the values without any data loss. I have read about Queues and the Producer/Consumer architecture but am not sure if it would really help in the current scenario any inputs on some relevant mechanism which would prevent such kind of data loss during transmission would be really helpful.

Thanks.

[James_McN]

Hi Harss,

First thing would be to confirm exactly where the problem is. As I mentioned before you would expect some samples missed on the FPGA when writing all of that data to the FIFO as it will take over 2us, but that does not necessarily mean that is the problem here, I would expect the write pattern you described to still work since you have 20us between the end of one trigger and the start of the next.

To confirm it is the network stream I would instead write the TDMS file on the RT target. That way you can compare the data, if it is still bad then you know it isn't the network stream. If it is OK then it is the network stream

[Harss]

Hi James,

Thanks a lot for your reply. It sounds like a good idea to first confirm if its an issue due to FPGA or Network Streams.

I had another question here , say incase it turns out to be an issue on the FPGA then I just needed some kind of direction as to how I should proceed because considering my FPGA VI . The details of the implementation are as follows

1:On the fourth frame of the Sequence Structure in the First While loop I generate the ADC sampling pulse for a duration of microseconds , it is at this point I start collecting timestamps into my local FIFO.

2:In the second While loop I do some processing to obtain valid chunks of 32 elements , this is in the form of an array and I together write these 32 elements (32 Sample Values) in the first FPGA to RT DMA FIFO , (32 Timestamp High values) in the second FPGA to RT DMA FIFO ,(32 Timestamp Low values) in the third FPGA to RT DMA FIFO .

Keeping this architecture as it is on the FPGA, just not writting anything to the FPGA to RT DMA FIFO in the second while loop, but in fact creating a third while loop below the second while loop to actually just write the single  values into the FPGA to RT DMA FIFO , but my question is how do I feed the values of the valid array elements I obtained into the second while to the third While loop for transportation purpose because if I use a Target DMA FIFO just for transportation purpose then I can write only single elements into it and not an array so indexing each and every element can again add to an overhead and I may loose some timing there probably take more than 2 microseconds. So could you please once again clarify as to How I transport these valid chunks obtained on the FPGA to the RT writting single element at a time onto the FPGA to RT DMA FIFO.

I have attached the snapshot of the FPGA VI.

Thanks once again.