Why do the LabVIEW examples that use the queue design have one loop in the top level and all the others as subvis?

[clendon.gibson@canrig.com]

Specifically the Weather Monitor example under connectivity/Web Services and the FPGA design examples.

There are several parallel loops. One of the parallel loops will be in the top level VI. The others are all in sub-VIs. After the third example I was looking at it seemed obvious this was being done as a standard, but I don't know why it matters.

Why not all of them as SubVIs? Why not all of them as top level loops? (Well OK maybe not that one.)

[tyk007]

My guess would be to keep the complexity of each block diagram down - encapsulating functionality into SubVIs - in order to make the example more easily understood. But yes, operationally (bar minor call overhead) it would be indentical.

[mikeporter]

More likely, they did one that way (for reasons unknown) and then they copied it for the other examples. There is no good reason for doing it that way.

Mike...

[crossrulz]

For me, it depends on what is happening in the parallel loops.  When I have modules that just need to run in parallel with the main loop, it helps reusability to have it a a subVI call.  I can then just copy that library to another project and use it.