What is the rate at which data samples are produced from a SIT connection manager

[NI_user_student]

Hello fellow Engineers!
I have a doubt regarding the use of SIT connection manager. I hope that some of you can help me by sharing useful tips and insights form your programming experience!
I have a simple application. I need to store a signal in excel sheet.

1. A .dll file is running in a Crio controller. This file has many output variables that produce signals which have to be stored. Let's look at one such output variable. This variable is mapped to communicate with my Labview VI via the SIT connection manager. This varable is a simple numeric indicator that produces the values of a signal.

2. I need to store one period/cycle of  a signal obtained from this variable in excel sheet.

I have implemented this algorithm already, but then I need to store 600 samples to store one period of the signal. I took the  SIT connection manager's sampling rate as 200 samples/second.  But, then, I find that 600 samples per signal is too much and memory ineffecient. I want to store lesser samples , but have the complete signal. I have the following doubts-


1. What is the exact sampling rate of the SIT connection manager. Is it decided by the 'base loop rate' or by the 'timer value' of 50 mS?
2. Is there a more memory effecient way of storing one complete period of a signal in excel sheet?
3. Can you suggest any clever method of storing signals without consuming too much memory?

I await your valuable inisghts and help,
With warm regards,
Aparna.

[SK@NIG]

Hi Aparna,

I try to answer your 3 questions below and add some details about the several timings when using the LV Simulation interface Toolkit.

1. What is the exact sampling rate of the SIT connection manager. Is it decided by the 'base loop rate' or by the 'timer value' of 50 mS?
What do you mean by sampling rate of the SIT connection manager?
The base loop is inside the driver VI (i.e. mymodel_driver.vi)
The base loop rate is dependant on your model/DLL timing. (--> Time for Hw I/O and model execution time must be less than the needed loop time, otherwise your algorithm will not be run as expected.)

The 'timer value' of 50ms - if I understood you correct - is the one in your  'SIT GUI' Vi.
This timer is inside the communication loop, that is responsible for the communication between the GUI and the Driver VI. The timing is just for decreasing CPU load on the Host system.
New simulation data will be transferred via TCP/IP between driverVI and the Host with this loop.


2. Is there a more memory effecient way of storing one complete period of a signal in excel sheet?
and
3. Can you suggest any clever method of storing signals without consuming too much memory?
You can use the Logging function of the SIT. The number of values / sample rate is equal to the model cycle time.
==> If you want to run your model with high sample rates, and log less samples , you can use the decimation factor in the SIT connection manager tab to reduce the amount of data.

Since SIT 4.0, in the SIT connection manager, you can switch between TXT or TMDS logging.
With the tdms data format, you are able to build several channel groups in one file, and choose different decimation factors for each group.
The tdms format is a very efficient method for storing data.
You find additional information for the tdms file structure - and also an Excel Addin if you need the data there.
http://zone.ni.com/devzone/cda/tut/p/id/3727

I hope this helps.

Have a nice day.

Stefan Kissel
Applications and Systems
NI Germany

[samweckx]

Hello,

I hope this fits a bit under this subject. I’m using SIT to run a simulink model on a Crio 9022 controller. This works good, until I try to decrease the fixed step solver in simulink below 0.001 seconds (1kHz). I need a sampling of more than 1kHz, but if I try to run with for example 5kHz, the Crio gives the next error.

Error 14120 occurred at Driver VI >> testtttt_Driver.vi >> testtttt_Base Rate Loop.vi >> NI_SIT_driversupportVIs.lvlib:SIT Take Model Time Step.vi:

Possible reason(s):

Simulation Interface Toolkit:  The base rate loop did not finish in time.  The combined time of computing the model and performing input and output is too long. Increase the model time step, switch to a simpler solver, or reduce the number of inputs and outputs used.

I tried already with really easy simulink models (with input/output), with easy solvers and he still generates this error. So the reasons suggested by the error message are probably not an option.

What should I do to solve this, or is this just a limitation of the SIT. Do I maybe have to change something in the FPGA bitfile? My input module is the NI 9201 and the output module NI 9263.

Thanks a lot,

Sam Weckx

[Arman Ans]

Hello,

I deployed the model to the CompactRIO, but the thing when I want to increase the solver fixed step size in Simulink more than 2500 Hz (0.0004) the driver VI send error that it is too big (Error 14120 occurred at Driver VI >> contr_Driver.vi >> contr_Base Rate Loop.vi >> NI_SIT_driversupportVIs.lvlib:SIT Take Model Time Step.vi:
)

I need to increase the step-size because the accuracy depends on step size.

Every advice will appriciated 

 Thank you.

Kind regards, Arman