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What is the best hardware&software combination?

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Hi, everyone!

 

 

I'd like to discuss the best combination for my control system with you.

 

1) Data sampling rate: 125~200kHz

2) Data is calcualted by several equations and there is a new value will be applied to a specific logic such as if structure.

 

ex)  x(i)= sample data  

       y(i)= calculated value                                  => if   0.2 <y(i)<1.3 ,  z(i)= 4.0 

       z(i)= defined value by if structre above.        

 

3) z(i) is applied to RT VI and RT VI sent z(i) value to FPGA VI.

 

 

The explanation above is somewhat plain to let you understand easily.

 

Could you recommend the best combination of NI hardware also software?  (How can I approah to my control system?

All advices are welcome!

 

Thank you.

Sincerely,

Hyo

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Care to be more specific with your equations?  If they are not that complex, I would recommend just putting all of the logic inside of an FPGA and avoid the RT, at least for the control part.  What other parts do you have in your system (logger, HMI communication, etc)?  What are the voltage and current levels of these signals?

 

As you might have noticed, you have not supplied nearly enough information to give any advice.


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As crossrulz has said, you have not provided nearly enough information to make any sort of educated suggestion. For example, I'm assuming you're measuring analogue signals, but how many? What is the voltage range?

 

If you don't need RT (because you can do the deterministic calculations/control on the FPGA), then you can use the NI FPGA only cRIO chassis (e.g. 9147 or 9149) with an appropriate C Series module for analogue input. You could also use a R Series RIO card which plugs into your PC (e.g. USB or PCI/PCIe) - but it's not as embedded/rugged as a cRIO.


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I'm really sorry about too long explanation.

All advices are welcome and thank you so much!!!

Sincerely,

Hyo

 

Steps

Data x(i) and y(i) sampling rates are same with 200kHz.

Data = x(i), y(i)

 

1 . R(i) = cos(x(i)) + (a+(sin(x(i))^2)^(-1/2)

2.  V(i) = b*[y(i)+y(i+1)]*[R(i+1)-R(i)]/[x(i+1)-x(i)] + c*[y(i)-y(i+1)]*[R(i+1)+R(i)]/[x(i+1)-x(i)]

3.  I(i) = integrate V(i) , i= 0 ~ i th

 

4.  When max i = 4000

     I_total = integrate I(i) ,  i=  0 ~ 4000 th

5.  Find g(1) = x(i) at I(i) = I_total/2

 

6.  Some codes will define a new control parameter for the next FPGA control.

     (This step is more complex than the codes indicated above.)

 

New control parameters produce new x(i) and y(i) set and do step 1~6 again.

 

** g(i) ~ g(i+4) values, the latest five values, should be saved to help define new control parameter for      

      FPGA control

** I have    (all data input module is possible to obtain x(i) and y(i) data)

SCB68 and PCI 6122 / BNC 2110 and PCI 6601 / cRIO chassis and modules for FPGA/RT control.

SCXI chassis and SCXI module.

 

Step 1 ~ 3 should be done in real time by using ????.

Step 4 ~ 6 should be done within 25ms after the last x(i) and y(i) value come

 

I think FPGA is not allowable to implement divisions. Is it right?

 

Seemingly, data acquisition can be done with one of data acquisition systems.

, but I don’t know how I can make the step 1 ~ 6 with the execution time limit.

How can I make step 1~6 ? and What is the best approach for the fastest calculation?

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Accepted by topic author catalysthw

Hi catalyst,

 

I have    (all data input module is possible to obtain x(i) and y(i) data)

SCB68 and PCI 6122 / BNC 2110 and PCI 6601 / cRIO chassis and modules for FPGA/RT control.

SCXI chassis and SCXI module.

- SCB68 and BNC2110 are just connector boxes and irrelevant for the question.

- PCI6122/6601 are DAQ hardware to be built into a (Windows) PC.

- You don't name your cRIO chassis nor the module you have available.

- You don't name the SCXI chassis nor the SCXI modules…

 

Step 1 ~ 3 should be done in real time by using ????

Why does it have to be "in realtime"?

I would just read 4000 samples (which means 20ms acquisition at 200kS/s) with DAQmx, then apply your math.

 

Step 4 ~ 6 should be done within 25ms after the last x(i) and y(i) value come

What is the "last x & y" value? Is it sample #3999 of your block of 4000 samples?

Why should it take more than 25ms to add up 4000 values and to search an element in this vector?

 

What is the best approach for the fastest calculation?

First: create an efficient algorithm.

Second: use the fastest CPU you can get…

(For me it doesn't make sense to acquire the data with your PCI6120 and to stream the  data for to cRIO-RT/FPGA to do the calculation over there. Network transfers will take more time than it needs to do the calculation on your PC…)

 

Please start with the "First" step. Attach your result and we will check for (speed) improvements… (Don't forget to attach your formulas in proper math layout.)

Best regards,
GerdW


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@catalysthw wrote:

I think FPGA is not allowable to implement divisions. Is it right?


FPGA can do division.  It just uses a lot of fabric.  Still, I don't see anything in there that couldn't be done in the FPGA.

 

But the simplest would be to just use a good computer and DAQmx to read that PCI board and do the math on the PC.


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Thank you so much!

 

Before updating more information, I'd like to check just one thing.

 

PCI - data process in computer by codes - New parameters - > RT or FPGA VI

Can I make new parameters from the codes in computer and apply the new parameters to FPGA or RT VI?

If it is possible, at least, I can verify that applying new parameters to FPGA or RT VI is implemented by computer.  

 

I will update more information you asked. Thank you so much again!

 

 

Sincerely,

Hyo

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Hi catalyst,

 

yes, it can be done.

Best regards,
GerdW


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