Varying Compilation Results in LabVIEW FPGA

[nmbernardo]

Hello. I would like to ask why LabVIEW FPGA generates different compilation results for the same code. When I repeatedly compile my code, the maximum speed and total slices of the generated bitfile changes according to the compilation report but I did not change anything with the FPGA VI. Also, Is the compilation report accurate? Thank you

[nathand · Accepted solution]

This is normal. The FPGA compiler starts placing pieces of code on the FPGA somewhat at random, and adjusts them until either the design fits and meets timing criteria, or it the compiler determines that it cannot fit all the code and meet the timing constraints. The outputs that the FPGA VI produces when run will still be the same.

[david1147]

Yes, this random starting point is controled by a random seed applied to Xilinx compilation tool. Technically, there is a way to fix this seed so that every time your compilation output is the same. However, LV FPGA currently doesn't expose this level of detail to users. However, if you are satisfied with your one-time compilation output, you can still store your bitfile and reuse that if you want.