Variable size array output from dynamic dispatch class method on FPGA

[Mmehrabin]

I have an FPGA and I need to have a variable array in it. Is that possible somehow?

Error:

"The FPGA Module does not support variable-sized arrays on the front panel of the top-level VI."

[natasftw]

I think you have a fundamental misundertanding of what FPGA coding is.

You write code and it looks like software.  It compiles into a bitfile that tells the FPGA how to configure the hardware processor to handle your task.  Once compiled, it's fixed.  How do you propose to have fixed hardware create the variable space?

No, it's not possible to have a variable sized array.  You'll want to find another solution.  Do you know the maximum size of your data?

[Mmehrabin]

I know what happen in FPGA and because of that I asked to implement it somehow.

I can assume a maximum size but it is not modular and a good code.

what is your idea about DMA FIFO? The major problem in DMA FIFO is that once you read an element from the FIFO, it is removed from the array whereas I need all elements to have process them several times. How about memory?

or send the data from FPGA to the Host VI to have the process by the target to host FIFO? regarding this matter, there is a variety limitation in FPGA to calculate or using some certain functions such as STFT (which I need to apply on FPGA data)