Hey all,
I'm running into a problem that I've not had much success searching online.
I've got a 9030 chassis with an FPGA built in, top-level clock 40MHz. I've got an NI-9401 DIO C-series module plugged into it and set to be managed by the FPGA target. I need to count some linear encoders at exactly 10MHz, no more, no less. They are clocked and give an output in such a way that if I oversample or undersample, I get garbage.
If I create a SCTL and set it to a derived timing source of 10MHz, I get a code generation error that:
"The Read FPGA I/O Node for DIO3 is used in a clock domain that it does not support. The supported clock domains include: the top-level clock and any clocks that have a rate that is a multiple of 40 MHz, such as 40 MHz, 80 MHz, 120 MHz, and so on."
I tried a few ways to get around this; first I tried just using a while loop with a loop timer set to 4 ticks, but it then takes 9 clock cycles to execute the counting for some reason (though this code can compile in the SCTL with no problems). I then tried using the SCTL with a "true" constant wired to STOP as a hack for a "timed sequence" frame, and that definitely did not work.
Are there any strategies or techniques or settings somewhere to get around this limitation on the DIO that I need to sample at exactly 10MHz? I would love to do this quickly in software and get this rolling ASAP.
An image of the relevant section of code is attached, I'm happy to provide more stuff upon request.
Many thanks!
Maia Bageant