Understanding FPGA FXP LMS.vi code

[charansai]

Hello everyone,

I am working on Active Noise Cancellation project. I need to implement fixed point LMS code on FPGA target of myRIO 1900. I know , I can generate this using FPGA Target > IP Generator. I could do that, but I have to modify that code a litlle bit, as I will directly get the error e signal from microphone and there is no desired signal d available.

I did some decoding and understood a bit of how it is working, but still could not understand some essential part of it! 

Below I will attach, the FXP LMS vi . There are also two subVIs needed which I cannot include here but I can add pictures of it if needed.

I could not understand, how this algorithm performs the Estimated signal step viz. [ y(n) = x_temp(n) vector * w(n) vector '  ; ]. I marked the section of the code where I am facing some problem in the attached picture. The algorithm does not show any clue how it is performing these vector operations.

I could not also understand, some logic with numbers that he has chosen like 8, 3 ,7 ,9 etc. 

Further clarifications on my understanding will be provided .

Any help in this problem will be appreciated.

PS: I could implement using memory blocks as basic array elements, like intialzing both x and w vectors. But eventually, I have to read and write several times, which is killing time.

[pfehlner]

Hey,

i have some questions concerning your project.

I can identifiy the "3" and "8" in the main.vi and in the subVI "aft_FXP_LMS_address_generator" the 9 and 7.

Am i assuming correctly that you mean those numbers with that phrase "some logic with numbers that he has chosen like 8, 3 ,7 ,9 etc." ?

As far as i see it these numbers and the subVI are just there to create addresses for the memory, but i m not quite sure.

Do you know where the ""aft_FXP_LMS_address_generator" comes from because i cant find that vi in the Digital Filter Design Toolkit, which includes the adaptive filters?

Additionally it would be nice to know what happens in your subVI to get a deeper understanding about your Code? Or is that some kind of example?

To the code in your red circle is there to pipeline your FPGA VI. More information on that you find in the following link

Optimizing FPGA VIs Using Pipelining (FPGA Module) - LabVIEW 2015 FPGA Module Help - National Instruments
http://zone.ni.com/reference/en-XX/help/371599L-01/lvfpgaconcepts/fpga_pipelining/

Greetings!

[charansai]

Hi there,

Additionally it would be nice to know what happens in your subVI to get a deeper understanding about your Code? Or is that some kind of example?

This Vi that I posted is not some example. It is Labview Generated fpga algorithm. To get this algorithm and sub VI , check this http://zone.ni.com/reference/en-XX/help/372357A-01/lvaft/aft_db_codegen/

 I will attach the sub VI that you are asking for below as .png file.

If you know LMS implementation in general, we will use vectors for x,w, y and so on and we will update the values and replace the previous values with new values. Here in fpga to implement LMS in 1 SCTL, we can not read write several times from memories nor we can use intialized vectors.(You might know all this already just to make my point ... )

What I mean by the ''logic with numbers 8,3,5,7,9'' is that, Its not a straight forward implementation of LMS, he is using reading address from w and x are different and writing address for w is also different.

Whereas  normally y(n) = x(n)w(0)+x(n-1)w(1)+x(n-2)w(2)+.....x(n-L+1)w(L-1); which is straight forward in the sense that 'x buffer vector( of lenght L)' will simply be multiplied by w vectror and added to get y values

He is following some sequential logic structure which is not so clear to me,as you said he might be using pipelining.Thanks for the link , I am not quite aware of pipelining.

I tried to break it, but ended up writing my own logic which is still working in 1 SCTL (still i am testing it ,sure of the logic but not so sure of few other things) .

Cheers 🙂

[charansai]

@pfehlner ,

The numbers make somewhat sense to me now, after reading about pipelining .  Thank you (y) .