Unable to achieve the desired timing Resolution with FPGA

[GerdW]

Hi Rohit,

on the FPGA you can access several channels/bits on your 9403 module blockwise!

They are grouped either in 8bits, 16bits or all 32bits:

This way you can update several channels with just one read/write access!

[James_McN]

Hi Rohit,

Pleased to hear you got to the bottom of it.

The 7us update is due to what Terry mentioned which is that the FPGA actually communicates with the module through SPI rather than a direct digital output.

I can't test this but based on other modules what I expect you will find is that running the IO block, it will take 7us to operate while it sends the SPI packet. This is how similar modules work. That is why you see the behaviour you see.

I believe this means that no, you could only update another channel after that 7us though I'm not 100% sure on this. I maybe mistaken though, if you did want to do this then I would guess at least you would need to use another IO node to do it.

[Rohit0729]

Thanks GerdW.

I did know that we can update several channels in one go.

But my practical situations are the following (I plan to use flat sequences):

Case 1: 

• Generate On signal from one channel of the 9403 module.
• Wait for about 7 us or less.
• Generate On signal from other channel of the 9403 module.
• Wait for about 7 us or less.
• Generate Off signal from this other channel of the 9403 module.
• Wait for about 7 us or less.
• Generate Off signal from the one channel of the 9403 module.

Case 2:

• Generate On signal from one channel of the 9403 module.
• Wait for about 7 us or less.
• Generate Off signal from this one channel of the 9403 module.

I do not want to update multiple channels together, but after a time delay (which I want to update in less than 7 us and want to see what is the least I can go in both Case 1 and 2 i.e. a controlled delay which is not possible (I think) if I choose to do only one read/write access for all).

Also, wherever I have written "Wait for about 7 us or less", I would like to know what is the minimum I can go in each case. I should have full control over the timing delay but I want to go as less as possible.

[Rohit0729]

Thanks James,

I have posted a reply in which I have described my task more. Can you please have a look? I will go through the SPI bus communication which you mentioned.