Triple module redundancy design

[m_mckee]

Hi,

Has anyone tried to implement 'Triple Module Redundancy' on an FPGA card? I have a PXI-7853R. I'm thinking that I can support only one bit file. Yes, I could write the three modules in a single bit file, but then, how would I control where  on the FPGA each module would be built.

Any ideas?

Thanks!

[Michael_78 · Accepted solution]

I had a similar requirement recently. I just dropped 2 coppies for dual redundancy knowing they would be compiled twice but I had no control over where they were compiled to. However I did find that by looking in the ucf file for the fpga (which is found with the labview fpga installation) and the fpga datasheet from xylinx I could identify io pins and at least have the io of my redundant logic located in different areas. I hope this is at least some use to you. Best of luck.
Michael