Transfer data from FPGA Target to RT, manipulate data in RT, send results back to FPGA

[NA_Kamaruz]

Hi.

I am using cRIO 9063.

In FPGA, I would like to read data from 6 analog input channels (NI 9205), then transfer the data to RT in order to perform arithmetic manipulation. Lastly, send the manipulated data from the RT to FPGA Target. This is required as the data needs to be used for PID Control in FPGA.

I read that DMA FIFO is useful for this application. So far, I created two DMA FIFOs; 1) Store the raw data from the analog input, 2) Store the final result of the arithmetic calculation. I have no problem in the first FIFO. The problem lies in the second FIFO (Calibrated sensor measurement), I cannot create a WRITE FIFO in the RT for storing the calculated results and also the READ FIFO (to read the calculated results from RT) in the FPGA.

I am attaching snippet of the FPGA and RT vi.

Please advise on how to do this.

Thanks,

NA

[GerdW]

Hi NA,

images are hard to debug, so please attach real VIs. As this seems to be a problem of the FIFO definition you need to attach the lvproj file too…

(Did you try to switch the "Read" method to "Write" on the RT VI?)

[Sam_Sharp]

Did you change the FIFO from a 'Target to Host' (FPGA to RT) to a 'Host to Target' (RT to FPGA) in the FIFO properties? You also need to use the correct method (e.g. Write).

[crossrulz]

From your pictures, I see no reason to even do the work in both the FPGA and RT.  All of the math can be done on the FPGA!  The only function you will have to dig a little for is the High Throughput Inverse Tangent.  But this will make things a lot simpler (less communications to worry about) and more reliable (can do the math at the exact same rate you read it and with less latency, making a more stable control loop).

[NA_Kamaruz]

At first, I did all the math in FPGA. However, when I tried compiling the FPGA vi. There was error due to exceeding the size of slice LUTs. That is why I am transferring my math to RT.

But then I realized, even after transferring the math to RT, the slice LUTs count is still over 100%. So, I guess I would keep the math in the FPGA vi and do changes elsewhere.

Thank you everyone!

[Sam_Sharp]

You should be able to optimise your FPGA code to make it possible.

There is an excellent resource somewhere on optimising FPGA code for speed/resource efficiency - have a search around. NI even have a course dedicated to it (High Throughput FPGA Course).

Here are some things you can try:
- Try to minimise divide operations as these are resource heavy. Multiply by 0.5 or 1/270 (0.003703 etc.) instead (yes, it makes a difference).
- Since all you're doing in the first part is a linear scale, you could use a single multiply & add function in a for loop (build array, for loop, index array). This will make your code run slower, but will use less resources. You could do the same for the trigonometric functions.
- When using fixed point numbers, be careful about the FPGA having to constantly move the fixed point, as this will use additional resources to line up the numbers before doing any operations

[crossrulz]

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@NA_Kamaruz wrote:

There was error due to exceeding the size of slice LUTs.

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What all do you have happening in that FPGA?  I have never come close to filling up an FPGA on my cRIOs.  Granted, I haven't had to do any expensive math in mine like some people here have.  But your simple formula should not be filling up the FPGA.