09-06-2016 10:14 PM
Hi.
I am using cRIO 9063.
In FPGA, I would like to read data from 6 analog input channels (NI 9205), then transfer the data to RT in order to perform arithmetic manipulation. Lastly, send the manipulated data from the RT to FPGA Target. This is required as the data needs to be used for PID Control in FPGA.
I read that DMA FIFO is useful for this application. So far, I created two DMA FIFOs; 1) Store the raw data from the analog input, 2) Store the final result of the arithmetic calculation. I have no problem in the first FIFO. The problem lies in the second FIFO (Calibrated sensor measurement), I cannot create a WRITE FIFO in the RT for storing the calculated results and also the READ FIFO (to read the calculated results from RT) in the FPGA.
I am attaching snippet of the FPGA and RT vi.
Please advise on how to do this.
Thanks,
NA
09-07-2016 01:00 AM - edited 09-07-2016 01:01 AM
09-07-2016 04:14 AM
09-07-2016 05:04 AM
From your pictures, I see no reason to even do the work in both the FPGA and RT. All of the math can be done on the FPGA! The only function you will have to dig a little for is the High Throughput Inverse Tangent. But this will make things a lot simpler (less communications to worry about) and more reliable (can do the math at the exact same rate you read it and with less latency, making a more stable control loop).
09-07-2016 08:12 PM
At first, I did all the math in FPGA. However, when I tried compiling the FPGA vi. There was error due to exceeding the size of slice LUTs. That is why I am transferring my math to RT.
But then I realized, even after transferring the math to RT, the slice LUTs count is still over 100%. So, I guess I would keep the math in the FPGA vi and do changes elsewhere.
Thank you everyone!
09-08-2016 03:40 AM
09-08-2016 12:51 PM
@NA_Kamaruz wrote:There was error due to exceeding the size of slice LUTs.
What all do you have happening in that FPGA? I have never come close to filling up an FPGA on my cRIOs. Granted, I haven't had to do any expensive math in mine like some people here have. But your simple formula should not be filling up the FPGA.