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Timed loop: Error -209801

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Hi, 

I am having some difficulties running a timed loop in LabView 2012 Service Pack 1. My goal is to use a rising edge coming from a camera to trigger the positioning of a piezo driven microscope stage. The camera sends it's trigger with a frequency between 30 and 120 Hz, depending on the camera's settings. The rise and fall times of the trigger are < 1 micro second, the width is between  32 - 42  micro seconds. The stage movement is done by setting an anlalog output voltage to a value proportional to the index of a timed loop (modulo some constant).


Now, Labview states that a DAQmx Write did not complete in time. This error is perfectly reproducible, and occurs whenever the loop index reaches 100. This is independent of the
frequency of the trigger and independently of the edge count set on the Timing Source used for the loop. Even if I set the trigger frequency to 30 Hz, and the edge count to 100, so that the loop body is run once every 3.3 s the same error occurs after 100 loop iterations. Tools»Profile»Performance and Memory reports zero time for all sub VIs.The independence of the actual timing leads me to believe this is not a timing issue per se, but that I am missing something and this is due to a synchronization issue between the write and the loop, or even an overflowing buffer.

This is the error I am getting when running  ExternalCounter.vi (attached)

Error -209801 occurred at ExternalCounter.vi

Possible reason(s):
DAQmx Write did not complete before the arrival of the next sample clock which indicates that your program is not keeping up with the hardware clock.
Slow down the hardware clock or else change your application so that it can keep up with the hardware clock.
Task Name: _unnamedTask<1C>

 

I'd be grateful for any hints on how to diagnose/resolve this issue.

 

Bastian

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Solution
Accepted by topic author BastianRa

Hi Bastian,

 

Your sample clock (1000 S/s) is running /updating faster than the timed loop at all the trigger frequencies (30Hz to 120Hz).

 

It means sample clock will arrive at some point in time at which there is no data to update. That is what you error also describes exactly.

 

Use the “Convert Late Errors To Warnings Property" as shown in the attachment and let me know.

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That did the trick,

Thanks a lot.

 

Bastian

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Hi,

I am setting up one test system using NI VeriStand 2013 SP1. I have simulink model and its dll generated for integration into VeriStand Environment. Simulink model caluculates voltage value for pressure sensor in the range of 0 to 5v and it is mapped to PXIe X Seriec 6341 Multifunction DAQ card. After deploying VeriStand project to RT Controller (PXIe8135 with PharLap RTOS), it works for some time but after some interval I see this error and project automatically gets un deployed:

*I am scheduling Simulink Model dll simulation at 1ms in VeriStand

* Target rate for Controller is 1000Hz

 

Error -209801

DAQmx Write did not complete before the arrival of the next sample clock which indicates that your program is not keeping up with the hardware clock. To remove this warning, slow down the hardware clock, or else change your application so that it can keep up with the hardware clock.

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Hi AmitSaste,

 

For future reference, it’s best to create a new thread than to post on an older forum, especially one marked as solved. This will ensure that it’s visible to the users on the community. Additionally, this would best be asked on our NI VeriStand forums as this question is more specific to VeriStand than to LabVIEW.

 

You may find some interesting information in this thread as well that mentions this error in conjunction with VeriStand:

http://forums.ni.com/t5/NI-VeriStand/209801-Error-at-high-speed/td-p/3035773.

 

It sounds as if your model loop is unable to keep up with the 1 kHz rate you are requesting. One way to check your loop rates is to monitor the HP Count and Model Count VeriStand System Channels. The HP Count will let you know if the entire PCL (Primary Control Loop) is running late. The Model Count will let you know if your model is running late. If your model count is increasing throughout the execution, it means that your model is not able to execute in 1 ms and provide the analog output with a new value each iteration of the sample clock which would explain the error.

 

Hope this helps!

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