Testing of IC's in a PCB using LabVIEW

[sumukh]

There is a PCB with a lot of IC's. The IC's are mainly buffers,SRAM,PROM, ASIC's, CPLD's and FPGA. None of them are JTAG compatible i.e. no TDI/O pins available. However only one CPLD is JTAG compatible. Is there a way through which I can test the functinality of these IC's using LabVIEW?

Without the JTAG interface, do I have any other medium through which my VI's can communicate with these memory IC's?

one more thing is that I cannot remove any of the IC's from the PCB, they have to be tested while they are present in the board itself.

[Ray.R]

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@sumukh wrote:

There is a PCB with a lot of IC's. The IC's are mainly buffers,SRAM,PROM, ASIC's, CPLD's and FPGA. None of them are JTAG compatible i.e. no TDI/O pins available. However only one CPLD is JTAG compatible. Is there a way through which I can test the functinality of these IC's using LabVIEW?--Yes

Without the JTAG interface, do I have any other medium through which my VI's can communicate with these memory IC's?  Not directly, of course.  You need to find out how you can communictae to the card.  Is it BDM, serial, USB, Ethernet, PCI, whaterver interface that allows to program PLD's, FLASH memory and can interface to the outside world.  LabVIEW can communicate with all that.  It may require additional hardware (BDM, JTAG, adapters).

one more thing is that I cannot remove any of the IC's from the PCB, they have to be tested while they are present in the board itself. Of course.. That is usually how they are tested once they are integrated into the board (system)

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It sounds like this is the first time you do this.

You need help beyond LabVIEW if that is the case.

You first need to identify how you can interface to the board.  That step is required regardless of what language youuse to develop test software.  The ahrdware designers should be able to help you with that.

[johnsold]

In addition to what Ray has already told you I would add that you will likely not be able to comprehensively test the ICs in an assembled board with the limitations you listed.  If you can get a good description of the inputs and expected outputs, (and that is a BIG IF), you may be able to do a reasonably good functional test on the board.

How fast is the board operating? What kinds of faults do you need to find? How many different configurations does each board have? ...

Lynn

[Ray.R]

Well said Lynn...

I wonder if the OP is trying to simulate a Boundary Scan... which... well... won't be possible..  But if the drivers provide BIST support to cover the chips, then calling the appropriate functions (or wrappers) should do the trick..

But the devices by themselves are just blocks of epoxy with metal pins sticking out (or solder balls underneath).  So LabVIEW cannot test devices directly.

It all depends on how in depth you want the test coverage to be and what capabilities were designed for test (DFT <<< very important).

[Karl_Miles]

The fact only one of the devices has a JTAG port, does not stop you testing more of the design. For instance if the RAM is connected to the CPLD then you can write and read to the RAM via Boundary Scan and confirm the interconnect to the RAM.

I'd be interested to look at your project, as 99% of FPGAs have a JTAG port.

I work for Goepel in the UK, www.goepel.co.uk but we have offices and distributors worldwide.

Very briefly, the normal way of testing a board and integrating it with Labview.

1.The Boundary Scan software generates the tests to be applied to the UUT via a Boundary Scan controller card (a lot of options at this point, ie interface (PXI, USB, LAN) and number of TAP ports/chains that need to be supported.

2.These tests can then be controlled via Labview or TestStand.

3.Where there are signals that come to a connector then you can use an IO card to stimulate or measure the IO, this can be digital or analogue (ie DAC or ADC) and the Boundary Scan can control the internals.

There is a cross over point, between where it makes sense to use Boundary Scan and where you shift to a functional test. Boundary Scan typically gives you better fault isolation and does not need software or firmware loaded. Functional test is normally still needed to prove the board is working before shipping to a customer but this is normally more a GO/NO GO rather than detailing where the issue lies.

[Karl_Miles]

If you want to simulate Boundary Scan at a board level, Goepel has a VHDL & Verilog output option from its Boundary Scan software.

[Ray.R]

Thank you for your reply monkeymiles,

We use Goepel where I work.

I was under the impression that you always need a license to run the software.

We use Cascon 4.5 for Boundary Scan development.

Are there other software that can be used for evaluation of JTAG implementation as you describe in your post?

[Karl_Miles]

You are correct that you would need a license to execute the tests with our hardware but there are many different license options. Once you have developed the tests, you just need a Test Station license (execution). This comes in three levels.

1.GO/NO GO (PASS/FAIL)

2.Diagnostic

3.Diagnostic and repair (includes pin toggler, debugger etc from the development station).

You can export tests in SVF (Serial Vector Format) but you would still need a piece of hardware to apply them and you would only get a GO/NO GO (PASS/FAIL) result. SVF can only be used for fixed pattern tests, ie if you have polling or conditionally statements then can't use SVF due to the format's limitations.

If you want to evaluate Boundary Scan, Goepel normally offers a 30 day trial of SW and HW.

In addition here in the UK we have an offer where we will do a test coverage report and DFT analysis for customers where they are unsure if Boundary Scan makes sense.

If it is more how Boundary Scan works, we have a free download "Scan Coach" at http://www.goepel.com/index.php?id=1418&L=4

If you want to check a BSDL file is valid without a SW license or uploading it to a website we also have another free piece of software, "BSDL Syntax Checker" which perfomrs BSDL syntax and semantics verification (IEEE1149.1, 1149.6 and 1532.). For some reason it has dropped off our main website at the moment, but if anybody direct messages me, I can send them a copy. 

[NIquist]

We haven't heard back from the OP but it sounds as if DFT wasn't a consideration in the design so even if ALL the chips were JTAG, boundary scan won't be an option since the necessary hardware lines were not designed into the PCB.  I suspect his only choice will be a functional test and LabVIEW is great for that.

[Karl_Miles]

DFT is quite often not a consideration but access to FPGA's and uP is, this is normally through a JTAG port and hence he will probably get good test coverage. When you combine that with Labview and IO modules to get excellent test coverage.

I've put together several PXI based systems under labview or teststand control, that start with Boundary Scan test, then programming then finally Functional test. Add in a mass interconnect from VPC or Macpanel and you have a very versatile test system.

As I stated earlier Functional test is great for telling you if a board works, but normally poor at isolating the actual faultly part or solder joint.

Really depends on what you are trying to achieve.