Synchronizing multiple FPGA PID loops

[watashin]

The PID gains that must be wired to the vi on the block diagram is Kp, Ki, and Kd (in FXP datatype), so Ki and Kd are always going to be zero if the Kp is zero. In other words, their definition of integral gain includes the proportional gain as well...

[nathand]

You are misunderstanding how the gains work. The gains that are wired from the block diagram are the normalized gains. The FPGA PID implementation is designed to be as efficient as possible, meaning it should not do the normalization calculation repeatedly. This is why the Express VI configuration does the normalization for you - so that it's done only once during setup, instead of adding FPGA code to compute it. The normalization calculation computes a new Ki based on proportional gain, integral time, and sampling time - but if you provide Ki yourself, then that's exactly the value that it uses in the PID algorithm.

This also matches the math explained in the help. Have you tested it?

[watashin]

I actually ended up making my own version of the PID FPGA vi, as I needed more resolution for the PID gains than the one that the built-in vi worked with. Everything works now! Either way, thank you for clarifying how the FPGA PID interprets the normalized gains, it definitely helped me understand the FPGA implementation of PID control better.

[johnsoja]

There really is a great deal of confusion for me surrounding the gain settings of the PID (FPGA) Express VI.  I use Matlab Simulink and tune my servo using that tool, which uses the classical parallel form PID approach (see attachment screenshot).  Assuming that in my Labview FPGA vi that I am assigning gains through a control box wired to the PID (FPGA) Express vi block gain input and it's running at 20KHz, I would like to have someone knowledgeable tell me what they would input into each gain field to effectively mimic the following Matlab parallel form PID gain settings.  In Matlab (Simulink) I'm using the Discrete PID block with a sample time of (1/20000), a P gain of 5, an I gain of 700, and a D gain of 0.  What are the equivalent settings for the Labview control block input into the PID FPGA Express vi block?

Also, I would like to have the precise equations that relate parallel form PID (Matlab) gains into the Labview PID FPGA Express VI gains.  I know that the Labview PID will allow an integral gain only (where P gain is 0) and it doesn't zero the output, but from the equations provided in the help it certainly appears as though it would.  Please explain.

Thanks,

JJ

[nathand]

---

@johnsoja wrote:

There really is a great deal of confusion for me...

---

Duplicate Post