11-17-2011 03:10 AM
Hi,
I recently installed LabVIEW 2011 with FPGA- and RT-Option. Now I allways have problems with compiling FGA-Code and get a xilinx error.
============================================================================================================
LabVIEW FPGA: The compilation failed due to a xilinx error.
Details:
ERROR:Place:665 - The design has 36 block-RAM components of which 5 block-RAM
components require the adjacent multiplier site to remain empty. This is
because certain input pins of adjacent block-RAM and multiplier sites share
routing ressources. In addition, the design has 36 multiplier components.
Therefore, the design would require a total of 41 multiplier sites on the
device. The current device has only 40 multiplier sites.
Phase 1.1 Initial Placement Analysis (Checksum:cc50394c) REAL time: 1 mins 51 secs
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.
Mapping completed.
See MAP report file "toplevel_gen_map.mrp" for details.
Problem encountered during the packing phase.
Design Summary
--------------
Number of errors : 2
Number of warnings : 115
Process "Map" failed
Start Time: 07:57:14
End Time: 09:07:05
Total Time: 01:09:51,468
==========================================================================================================
The code was built with LabVIEW 8.6 and worked fine with an cRIO 9074 for years now.
Since installing LabVIEW 2011 the Errors above occur.
Until now the cRIO 9074 was sufficient, it is the same code, so why is the space not enough with the new Version of the Xilinx Tool 12.4 ?
I would be glad if someone can give me an answer.
Thanks for your help
05-03-2013 08:24 AM
Did you come to know the reason?