01-28-2014 05:16 AM
@nathand i'm guessing that working with one element (read from the FIFO) should be fine? I'm not actually usign an array anywhere on the FPGA.
01-28-2014 12:58 PM
Ha! I would gladly take a beer. Sadly the Kudos button will have to do
So, it's important to remember that DMA actually involves 2 buffers. One of these buffers is on the Host side, and the other is on the FPGA side.
In the example, the HOST loop is stopped when the FIFO write times out. This means that the Host side buffer is full (the FPGA isn't reading fast enough), and we have an overflow scenario.
The FPGA VI is never stopped. Instead, it will time out when there is no data in the FPGA side buffer to be read, and we have an underflow scenario. This is handled in the FPGA VI by simply not processing the data that comes out of the FIFO when it's in a timed out state (the true case of the case structure has nothing in it).
Here's some fancy marketing slides (e.g, comlpete with animations) to show how DMA works 🙂
The slides show Target-to-Host communication, but it's really the same the other direction too (and it's the same idea for cRIO if that's your platform).