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State Machine Initialization in LabVIEW FPGA for Producing an External Gate and Clock

I am trying to construct an FPGA code that will produce a gate and two clocks using the DO of a PXIe-7962 with the 5751 output module. I am using a state machine so I can add additional states in the future. I have attached a picture of the FPGA code showing the two states and the subVI, which is a counter. I am triggering the start of the gate with the PXI_Trig0, but have also tried using just a front panel button and found the same results described below. The gate and clock should run once when triggered then sit and wait for any additional triggers.

 

I am looking at the output of two of the DO lines on a scope so I should see a gate and a square wave signal. When triggered, I get the output showing in TEK00130.jpg. Here there are two gated periods, but there should only be one. The first is not the correct length of time and its width seems to change depending on the length of time I used in the previous shot. The second image from the scope (TEK00131.jpg) shows what happens when the host machine never sends the PXI_Trig0. I still see an output from the DO despite never sending a trigger.

 

It seems like the trigger state is executing once before it receives PXI_Trig0 using data from a previous run, but I don't know why. How do I properly initialize the state so that I don't get this anamolous initial pulse out of the digital lines.

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You need to add a reset input to your counter. This should link to a case inside the counter that sticks a zero in the count. You then need to arrange for a TRUE to be sent to the reset when the triggered state is first entered and false thereafter.

 

e.g.

IF current_state=triggered & previous_State=waiting

        reset=TRUE

ELSE

        reset=FALSE

ENDIF

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