Slowdown of FIFOs when performing multiple cRIO simulations - are FIFOs not reentrant?

[Chris_12345]

I am simulating multiple cRIO chassis on a single multi-core machine, and have come across a problem with the FPGA FIFOs. A single simulation works fine, but when I have several simulations running in parallel, the FIFOs are considerably slower. I've put together a very simple example that demonstrates this, see attached. It seems like the FIFO is not re-entrant. Is there a way to change this behavior? My goal is to have a large number of simulations running, but I am currently limited to just 2 or 3 due to this FIFO slowdown. Any help would be appreciated. Thanks.

[JoeySpinella]

Hi Chris,

Thanks for taking the time to make an example project that clearly shows the problem you are seeing. When running on single mode, I see that the delay stays at around 30 ticks. When the Main vi is run on "Multi", I see a spike at the beginning, followed by a return to the delay levels we see for just one DMA FIFO. Because I was curious, I changed the delay in the FIFO_Read subVI to various ms values to see if it affected the average delay. 

Here were my results:

Wait function (ms), Average delay (ticks), Multi spike (ticks)
1000, 50, 2000
500, 30, 2200
200, 20, 1200-2300
100, 10, 1500

Is this the performance that you are seeing as well? I noted that at some points my CPU utilization would spike to 40%. It seems like after the initial spike, the simulated Multi-target DMA FIFOs are able to run at a speed similar to a single target. Also, what version of LabVIEW/RT/FPGA do you have installed?