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Simple Time Delay in FPGA (cRIO 9073)

Re: Simple Time Delay in FPGA (cRIO 9073)

‎08-28-2009 09:23 AM

Hi all,

 

Actually i tried the SCL but it doesn't work.

 

I think that the problem is in the => comparision.

 

I can send the VI if someone have a cRIO to reproduce the failure.

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Re: Simple Time Delay in FPGA (cRIO 9073)

‎08-28-2009 11:02 AM

You can post a zip file with your project on the forum and I can probably find time to look at it.  What version of LabVIEW is this?  I'm assuming you looked into everything in my last post already.  It doesn't make any sense that the comparison only fails when the VI is loaded from the the 9073's flash.  There's something else going on here.
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