Serial I/O IRQ Method

[csduffey]

I am trying to do some simple I/O using an NI 9870 serial module in a cRIO with a NI-9014 host (LabVIEW 9, RIO 3.2.1) .  I am already using 3 DMA FIFO's for other things and was trying to pass the data in and out of the FPGA using an interrupt driven approach.  The baud rate is 57600 which if you do the calculations is ~60 characters in 15 milliseconds.  So here is what I tried and the RT Host immediately stops running after the timeout -  I realize there are all sorts of unhandled conditions in this code but it won't even eat one character....

So here is the FPGA side - there is a pre-allocated array of 255 elements - the loop runs until the array is nearly full or a timeout occurs - at which point an interrupt is generated -

Here is the host side - wait for an IRQ and then read the array, after that ack the IRQ -

Am I missing something simple ?????

[csduffey]

BTW I realize in the diagrams that the acknowledge IRQ is inside the case satement - it should be out of it, I put it there to try and stop it from crashing the RT host while troubleshooting

[Anna_K.]

Hello, is your wait function on the FPGA set to mSec or uSec or ticks? If its set to mSec then you will have your FPGA code wait 15 ms before even executing the second frame of the sequence so you will reach a timeout on the wait on IRQ every time (when set to 5 ms).

Also, I suggest having a stop control wired to the Stop Terminal of your host loop rather than a true constant so that you can manually stop the loop and have the code complete  ( including closing the FPGA VI reference which I assume is sitting right outside your while loop. This Close FPGA Reference stops your FPGA code and cleans up the reference.

[William1225]

Hi

Sorry to reply this old article, but this issue happened to me recently.

I have a cRIO 9075 & NI 9871 to develop a project so I looked for the example of "NI 987x-Serial Loopback" to study first.

However, there are some details I can't figure out clearly.

The following image is code from FPGA,

It seems it would update the "Byte to Write" and transmit by FPGA, and then send the interrupt to notify the Host.

The following is the write part of the code from the Host(RT).

It will update the Op Control to write case, and update the "Byte to Write".

My question is what happened if the Write Byte Node in the FPGA code timed out?

In this example, it sets the timeout of the "Write Byte" to 100ms, but if RT is slow, say 1 second, to send the "Byte to Write" to the FPGA, it should be timeout, but I don't know what's the consequence.

I found out the reference http://zone.ni.com/reference/en-XX/help/370984R-01/lvaddon11/crio-9870/

It mentions that if no data is available, it will keep retrying!!!

As a result, it will retry and retry until the "Byte to Write" being updated in the RT code?

I tried to make my question clear enough, if there's something confused to you in my description, please let me know, I would try my best to explain more.

[GiantDeathRobot]

Hi William1225,

As you noted, this thread is six years old. You will get better visibility and more likely get help from the community if you post this in a new thread, especially since this is not exactly the same issue as the original thread.

[William1225]

Hi GiantDeathRobot,

Very thanks for your friendly reminder, I agree I should post a new thread to get more feedbacks:)

[GiantDeathRobot]

No problem! The way the forums sorts threads, new threads show up higher than old threads. Plus, your problem gets visibility in the title. 🙂